Push-type scheduling for semiconductor fabrication

Details Push-type scheduling for semiconductor fabrication Push-type scheduling for semiconductor fabrication

2000-02-28

2004-03-30

Picard, Leo (Department: 2125)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S100000, C700S121000

Reexamination Certificate

active

06714830

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to control of a production line for semiconductor fabrication. More particularly, the present invention concerns control for a semiconductor production line that queues work-in-process (WIP) before a re-entrant bottleneck processing node (such as a photo-lithographer), with the control utilizing a push-type method for sending WIP to subsequent processing nodes for processing after a determination has been made that a cleared trajectory through all subsequent processing nodes back to the re-entrant process is available and after the subsequent processing nodes have been reserved for the trajectory.
2. Description of the Related Art
Semiconductor fabrication is generally performed in a re-entrant production line consisting of a network of processing nodes. The production line is re-entrant in that a single WIP is processed multiple times by at least one of the processing nodes, usually a photolithography node. Due to a lack of control over WIP entering a queue for the re-entrant node, the re-entrant node often becomes a bottleneck in the processing network. The bottleneck results in inefficiencies in the production line utilization; inefficiencies that result in increased cost of both ownership and operation of the production line.
Additionally, subsequent processing nodes following the photolithography node can decrease the efficiency of the production line. These subsequent processing nodes perform manufacturing functions such as implantation, etching, metrology, oxidation, and so forth. Given the small amount of control over the actual WIP and these subsequent processing nodes, secondary bottlenecks can form in the production line leading to further inefficiencies. In addition, re-tooling and setup times of the various process machinery at the nodes can further increase the inefficiency.
These inefficiencies increase the cost of ownership and operation of the entire network. Therefore, maximizing the utilization of the bottleneck process, as well as reducing secondary bottlenecks, would improve the throughput of the network as a whole and minimize the cost of ownership.
Unfortunately, developing an optimal schedule for such a production facility can be very complex due to the number of steps involved and the possible combinations of those steps. Due to the complex computations involved in developing a schedule, real-time adjustments to the schedule can be very difficult.
Some effort has been made to resolve this problem and to increase the throughput of the production line. For example, U.S. Pat. No. 5,889,673, entitled “Manufacturing Method And System For Dynamic Dispatching Of Integrated Circuit Wafer Lots”, utilizes a method for dynamic dispatching of integrated circuit wafer lots (product). According to the patent, loading factors of machines downstream of the lithography machine, or descendent machines, are calculated to determine the machine with the lowest estimated loading value. That machine is then given the highest priority and the wafer lots are dispatched to that machine after the lithography process.
Therefore, the method of U.S. Pat. No. 5,889,673 addresses selection of which machine the product is sent to after the lithography process, in order to ensure that each downstream machine is adequately loaded. However, this method does not guarantee that the product will be processed by each downstream machine immediately upon the product arriving at the machine. As a result, secondary bottlenecks are still likely to occur.
Another attempt to reduce secondary bottlenecks is described in U.S. Pat. No. 5,446,671, entitled “Look-Ahead Method For Maintaining Optimum Queued Quantities Of In-Process Parts At A Manufacturing Bottleneck”. According to the patent, a look-ahead method monitors the product queued in all potential bottleneck processing nodes in the factory. A flag status is set at the queue of each potential bottleneck process to prevent product from being started until the queue at the bottleneck process has declined to a sufficiently low point as determined by factory management personnel. Thus product pile-up at the bottleneck queues is reduced.
However, like U.S. Pat. No. 5,889,673, the method of U.S. Pat. No. 5,446,671 also does not guarantee that the product will be processed through all processing nodes immediately upon receipt of the product at the node. Thus, with this method a secondary bottleneck is still present with the amount of product in the bottleneck queue having merely been reduced.
The importance of addressing bottleneck queues is particularly illustrated in the process of manufacturing semiconductors. Generally, in a semiconductor manufacturing facility, a semiconductor is produced by an initial product, such as a single wafer, being processed through a series of processing nodes to form a finished product. Each processing node in the series generally performs a different processing task. For example, the manufacturing facility may contain a series of processing nodes where each node is respectively dedicated to performing lithography, implantation, etching, metrology, or oxidation. The processing through each process may be linear with any particular process or processing node being visited only once. Alternatively, there may be a series of loops where a wafer is routed through the same processing node multiple times. The linear model is typical of a manufacturing production line where processing nodes or processes are set out in a definite order, while the loop model is typical of a production line where processing nodes are used as needed, depending upon the product. In the latter case, the product being processed may be re-entrant into the conceptual production line if one machine is used more than once.
In the present invention, one possible production method concerns a general network of processing nodes with no restrictions on the order of processing or the number of processes needed to finish a job. Also, no restriction is placed on the number or type of entry or exit nodes in the network. In a limiting case, a route through an isolated network of n nodes is equivalent to routes covering a complete directed graph (digraph) of N vertices and N(N−1) edges. A dynamic path through multiple nodes from one defined node to another defined node is referred to as a trajectory T(j,t
j
), where j is an ordered set of nodes and t
j
is a set of arrival times.
In a series of processing nodes, at least one type of processing node will generally be a bottleneck. The bottleneck may exist for a variety of reasons. For example, the length of a task being performed at the node may be longer than other processes or the node may be revisited multiple times. Also the cost of the bottleneck processor and/or the cost of operating the bottleneck processor may be very expensive, thereby limiting the number of those processors that may be employed in the network. Therefore, the cost of operating the processing network could be somewhat minimized by maximizing utilization of the bottleneck process. That is, improving the throughput of the bottleneck process would improve the throughput of the network as a whole, thereby reducing the cost of ownership of the entire network. However, improving the throughput of the bottleneck process alone may not lower the cost of ownership of the entire network where, for example, there is extreme under-utilization of less expensive processors.
Many manufacturing networks are finite source queuing networks where jobs are added to the system by considering the maximum number of jobs in the system. A description of finite source queuing networks can be found in Xiuli Chao, et al., “Queuing Networks: Customers, Signals and Product Form Solutions”, pp. 219-221, 1999, Wiley. Under these circumstances, the arrival rate may be defined as:
&lgr;(
n
)=0 for
n≧M
  (1)
&lgr;(n) is positive and finite for n≦M−1, where M is a positive integer. In this case, M is the number of jobs the system can hold.
The stationary dist

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