Push-pull switching circuit with minority carrier storage delay

Details Push-pull switching circuit with minority carrier storage delay Push-pull switching circuit with minority carrier storage delay

1977-02-01

1978-06-13

Miller, Jr., Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307218, 307247R, 307300, 330270, H03K 1760, H03F 326

Patent

active

040951286

ABSTRACT:
A push-pull switching circuit including two grounded emitter transistors 5, 6 controlled by a pair of AND gates 3, 4. The collector output of each transistor is fed back to an input of the AND gate controlling the other transistor, the remaining AND gate inputs being supplied by the Q and Q outputs of a flip-flop circuit 2. During the prolonged conduction of each transistor due to minority carrier storage, its lowered collector potential prevents the enabled AND gate for the other transistor from raising its output and initiating conduction, thereby avoiding overlapping or simultaneous transistor conduction.

REFERENCES:
patent: 2892103 (1959-06-01), Scarbrough
patent: 3418494 (1968-12-01), Reid
patent: 3490027 (1970-01-01), Galetto et al.
patent: 3538353 (1970-11-01), Hanger

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