Push-pull output stage of integrated circuit for reducing ground

Details Push-pull output stage of integrated circuit for reducing ground Push-pull output stage of integrated circuit for reducing ground

1990-02-15

1991-07-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307448, 307473, 307594, 307596, 323315, H03K 3013, H03K 513, H03K 1728, H03K 17687

Patent

active

050346377

ABSTRACT:
A push-pull output stage of an integrated circuit for generating a pulse-like output signal in dependence upon a pulse-like input signal. The integrated circuit of which the push-pull output stage is a part is susceptible to high switching speeds in which the pulse-like signal varies between high and low voltage levels. The push-pull output stage inhibits the overshoot of the pulse-like signal leading to inaccurate interpretation of the pulse-like signal as having a high voltage level when the pulse-like signal actually has a low voltage level. The output stage includes output field-effect transistors comprising two groups (12, 14) of parallel-connected subtransistors (TN1 to TNn, TP1 to TPn). The gate zones of the subtransistors in each respective group are connected together. To the gate zones of the subtransistors (TN1 to TNn) of at least one (12) of the two groups (12, 14) a current dissipating or grounding transistor (TS1) is connected. The current grounding transistor (TS1) is the output transistor of a current mirror circuit (TS1, TS2, TS3, TS4) which is made up solely of field-effect transistors and to the input transistor (TS2) of which a current dependent on the input signal is supplied for controlling the current grounding transistor (TS1).

REFERENCES:
patent: 4771195 (1988-09-01), Stein
patent: 4785201 (1988-11-01), Martinez
patent: 4789793 (1988-12-01), Ehni et al.
patent: 4820942 (1989-04-01), Chan
patent: 4885485 (1989-12-01), Leake et al.
patent: 4908528 (1990-03-01), Huang
patent: 4918339 (1990-04-01), Shigeo et al.
patent: 4961010 (1990-10-01), Davis
Advanced CMOS Logic, Designers Handbook, chapters 3.1.5, pp. 9-11, 1987.

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