Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-03-20
2002-10-15
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S170000, C326S083000
Reexamination Certificate
active
06466063
ABSTRACT:
FIELD OF THE INVENTION
The present invention broadly relates to output buffers used to reduce current and voltage spikes produced by power transistors, and deals more particularly with an output buffer having a gate voltage feedback loop for controlling slew rate and reducing crowbar current.
BACKGROUND OF THE INVENTION
Output buffers are used in integrated circuits to drive external loads. Typically the size of the load is not always known in advance, consequentially most output buffers are designed to provide enough current to drive loads up to a maximum permissible level. This is normally accomplished by providing an output transistor that is large enough to drive the maximum permissible load, and by providing a number of smaller transistors coupled in parallel to drive that maximum load.
Continuing advancements in integrated circuit technology have lead to improvements in the speed of integrated circuits, i.e. the time in which the output of a circuit reacts in response to a new input. Increasing integrated circuit speed had resulted in faster rise and fall times of the output voltage. Similarly, the fast rise and fall times of the output voltage result in abrupt transitions in output current. In the case of output buffers used with power transistors, a problem is encountered when the output buffer is quickly turned on or off. Because the current flow is so large, fast switching of prior art buffers can produce transients such as noise spikes on the power, ground or data busses, which result in data errors, latch-up and other problems in digital electronic circuitry.
One solution to this problem involves a technique referred to as slew-rate control. Slew-rate control is designed as the rate of output transition of the buffer in terms of volts per unit time. Conventional digital buffers with slew-rate control use a number of parallel transistors which can be sequentially turned on the reduce the abruptness of the transition and thereby reduce the above mentioned transients.
The transistor section of a digital output buffer can be arranged as a network which can pull up the output of a buffer to a certain voltage level, and a pull-down network which can pull down the output of the buffer to a different, lower voltage. Such an arrangement is sometimes referred to a push-pull output buffer. Because of the time delay involved in sequentially turning on the transistors of each network, a problem is sometimes encountered with slew-rate control when one of the networks of the buffers is being slowly turned on while the other network of the buffer is being slowly being turned off. The problem resides in the fact that for a brief period of time, both networks are turned on. In other words, the network being turned on becomes active before the network being turned off completes its turn-off sequence. As a result, during the period that both networks are active, a very large current known as a “crowbar” current is allowed to flow.
Known prior art arrangements for achieving slew-rate control and reduction of crowbar current have been relatively complicated in terms of the number of components that are required, and have been less than completely effective in providing the requisite level of control. The present invention is directed towards overcoming the disadvantages of the prior art mentioned above.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a push-pull output buffer has a pull-up section, a pull-down section, and a slew-rate control circuit associated with each of the pull-up, pull-down sections for controlling current drivers that control the flow of current at the buffer output. The slew-rate control circuit includes a first voltage supply circuit for supplying an intermediate level of voltage to the current driver, a second voltage supply circuit for supplying a second, higher level of control voltage to the current driver, a delay circuit for delaying the delivery of the second level of voltage to the driver for a prescribed time period, and a logic circuit for controlling the first and second voltage supply circuits so as to achieve a desired slew-rate, while minimizing the flow of any crow bar current. The first voltage supply circuit is preferably in the form of a deep voltage feedback loop that includes transistorized switches for switching a first voltage source into circuit with the gate of the current driver when a network is switched on. The second voltage supply circuit includes a transistorized first gate controlled by the logic circuit and operative to switch a higher level of voltage into circuit with gate of the current driver after a desired time delay following turn on of the network. The delay circuit includes a delay line formed by delay elements that delay the propagation of a control signal that enables the second supply circuit to switch the current driver to a higher voltage level. A one-way switch circuit is used to isolate the delay circuit from the feedback loop to prevent interference there between.
According to another aspect of the invention, a push-pull output buffer is provided for use with an integrated circuit, having an input and an output for driving a load. The buffer includes a pull-up section, a pull-down section and a slew-rate control circuit associated with each of the pull-up and pull-down sections. The pull-up and pull-down sections each include a current driver having a control gate. The slew-rate control circuit controls the rate at which the associated current driver changes the voltage at the buffer output. The slew-rate control circuit includes a gate voltage feedback loop circuit coupled with the driver's control gate for controlling such control gate with a first level voltage, a voltage source for supplying a second level of voltage higher than the first level, a switch circuit for switching a voltage source into circuit with the control gate and a delay circuit for delaying the delivery of the second level of voltage to the control gate.
Accordingly, it is a primary object of the present invention to provide an output buffer for a current producing device such as a CMOS device which includes improved slew-rate control and reduction of crowbar current.
Another object of the invention is to provide an output buffer as described above which provides greater control over the timing of the slew-rate using a minimum number of circuit components.
A still further object of the invention is to provide an output buffer of the type mentioned which is especially simple in design and can be laid out for simplified processing during manufacture thereof.
These, and further objects and advantages of the present invention will be made clear or will become apparent during the course of the following description of a preferred embodiment of the invention.
REFERENCES:
patent: 5877647 (1999-03-01), Vajapey et al.
patent: 6054875 (2000-04-01), Wayner
Taiwan Semiconductor Manufacturing Co. Ltd.
Tung & Associates
Wells Kenneth B.
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