Push-pull cascode logic

Details Push-pull cascode logic Push-pull cascode logic

1990-01-04

1991-06-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307279, 307530, 307362, 307481, H03K 5153, H03F 345

Patent

active

050234803

ABSTRACT:
A cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-coupled P-channel output transistors. The output nodes are connected to outputs of an N-channel combinatorial network that receives a differential input and functions to connect one of the output nodes to a positive supply and the other to ground, depending upon the differential input, thus providing a push-pull effect. The output nodes may be connected to the differential output of the combinatorial network by source-drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive supply to capacitively isolate the output nodes from the combinatorial network; alternatively, the gates of these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel transistors connecting the output nodes to ground, so the low side of the output is held down instead of being allowed to float. The channel types of the transistors may be reversed in another embodiment; the pull-down transistors of the differential amplifier may be N-channel and the logic and latching transistors P-channel.

REFERENCES:
patent: 4631424 (1986-12-01), Miyagi
patent: 4695744 (1987-09-01), Giordano
patent: 4739198 (1988-04-01), Maruyama
patent: 4816706 (1989-03-01), Dhong et al.
patent: 4833347 (1989-05-01), Rabe
patent: 4864159 (1989-09-01), Cornelissen
patent: 4929853 (1990-05-01), Kim et al.
Heller et al, "Cascode Voltage Switch Logic: A Differential CMOS Logic Family", ISSCC 84, Feb. 24, 1984, pp. 16-17.

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