Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
1999-12-27
2002-04-30
Shingleton, Michael B (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S264000, C330S267000, C330S051000
Reexamination Certificate
active
06380808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a push-pull amplifier circuit for amplifying an AC signal with controlling an idling current of its output stage.
2. Description of the Related Art
FIG. 20
shows a prior art push-pull amplifier of class AB, which is used, for example, in amplification of an audio signal and provides the amplified signal to a speaker. When the push-pull amplifier is used, for example, in mobile electronic equipment such as a portable telephone, high power efficiency and the lowest possible power consumption are demanded.
In the output stage of the circuit, an N-channel FET
10
and a P-channel FET
11
are connected in series between a conductor having a power supply potential VDD and a conductor having a power supply potential VSS. Currents IP and IN flowing through the transistors
10
and
11
are determined by gate potentials VG
1
and VG
2
of the transistors
10
and
11
, respectively.
In the input stage of the circuit, a constant current source
12
, an N-channel FET
13
, a P-channel FET
14
, and an N-channel FET
15
are connected in series between the conductor having the potential VDD and the conductor having the potential VSS.
The gate and drain of the N-channel FET
13
are mutually connected and the gate of the N-channel FET
13
is connected to the gate of the N-channel FET
10
. The gate and drain of the P-channel FET
14
are mutually connected and the gate of the P-channel FET
14
is connected to the gate of the P-channel FET
11
. A voltage between the gate and source of the N-channel FET
13
is substantially equal to the threshold voltage Vthn thereof and a voltage between the gate and source of the P-channel FET
14
is substantially equal to the threshold voltage Vthp thereof. Accordingly, a difference (VG
1
−VG
2
) between the gate potentials VG
1
and VG
2
of the transistors
10
and
11
is substantially constant independently of an input potential VI, having a signal and a bias voltage components, that is applied to the gate of the N-channel FET
15
. The transistors
13
and
14
constitute gate potential difference circuit
16
.
By means of the constant current source
12
, a substantially constant current ID flows through the between-gate potential difference circuit
16
and the N-channel FET
15
. The voltage VD between the source and drain of the constant current source
12
changes depending on the gate potential VI of the N-channel FET
15
, and VG
1
=VDD−VD is determined by VD. The constant current source
12
and the N-channel FET
15
constitute an input circuit
17
.
With rise in the input voltage VI from a value, the drain current ID of the constant current source
12
is going to increase, and the voltage VD between the source and drain of the constant current source
12
rises (see FIG.
21
(A)). Thereby, the gate potentials VG
1
and VG
2
each fall, resulting in decreasing in the current IP, increasing in the current IN and falling in output voltage VO.
One end of a load
18
is connected to a node between the N-channel FET
10
and the P-channel FET
11
, and the other end thereof is connected to a conductor having a power supply potential, for example, (VDD+VSS)/2. A current IL=IP−IN flows through the load
18
. When IP>IN, that is IL>0, an idle current flowing from VDD through the transistors
10
and
11
to VSS is equal to IN. When IP<IN, that is IL<0, an idle current flowing from VDD through the transistors
10
and
11
to VSS is equal to IP. Relations of each of the current IP and IN with the input voltage VI are as shown in FIG.
21
(B).
The idle current is required to have a magnitude at some extent in order to improve a linearity of the output signal with the input signal. The idle current generally tends to increase as the output current IL decreases (FIG.
21
(B)). Further, since the idle current changes depending on deviations of process in device fabrication and of temperature in operating, the minimum idle current has to be ensured in design so as to be more than a predetermined value in the worst conditions conceivable. Therefore, according to conditions, wasteful idle current flows which causes increase in power consumption. Especially, an idle current in the output stage of a push-pull amplifier cannot be neglected because its magnitude is rather large.
In order to decrease the idle current, in a push-pull amplifier disclosed in JP 96-23247A, the idle current is detected in a monitoring part having current mirror circuits, its detected value is compared with a current of a constant current source and the idle current is controlled so as to be of a predetermined value in response to the compared result.
In the output stage of that push-pull amplifier, as shown in
FIG. 22
, an N-channel FET
10
and a P-channel FET
11
are connected between conductors having a power supply potentials VDD and VSS in series in the order reverse to the case of FIG.
20
. The P-channel FET
11
and a P-channel FET
14
whose gate and drain are connected mutually constitute a current mirror circuit, and therefore a voltage between the source and gate of the P-channel FET
14
is substantially equal to the threshold voltage Vthp thereof. Likewise, the N-channel FET
10
and an N-channel FET
13
whose gate and drain are connected mutually constitute a current mirror circuit and therefore, a voltage between the source and gate of the N-channel FET
13
is substantially equal to the threshold voltage Vthn thereof. For example, in a case where the power supply voltage (VDD−VSS) is 3.0 V and the threshold voltages Vthp and Vthn are both 0.5 V, a potential difference between the gates of the transistors
11
and
10
are approximately 3.0−0.5×2=2.0 V regardless of an input signal.
However, when the power supply voltage (VDD−VSS) changes, the potential difference between the gates of the transistors
11
and
10
changes in a slave manner following the change in the power voltage (VDD−VSS). Therefore it becomes hard to control the idle current so as to be a predetermined value.
Further, letting &mgr;=(W/L of the transistor
11
)/(W/L of the transistor
14
), where a gate width is W and a gate length is L, the maximum value of the current IP flowing through the transistor
11
is limited to a value of &mgr; times the maximum current flowing through the transistor
14
. Since a size of the transistor
11
has a limit on its size, the maximum value of the current IP is also limited to a value under the limitation on the size. This limitation applies to the current IN as well.
Referring back to the push-pull amplifier of
FIG. 20
, the current IP is controlled by the voltage between the gate and source of the N-channel FET
10
. However, with rising in the gate potential VG
1
, an output voltage VO also rises. Therefore, the voltage between the gate and source is approximately equal to the threshold voltage Vthn of the N-channel FET
10
, resulting in that the maximum value of the current IP is limited. This limitation also applies to the current IN.
In addition, in the push-pull amplifier of
FIG. 20
, the maximum amplitude of the output voltage VO is limited in the following way. That is, since a relation VO≈VDD−VD−Vthn holds, the minimum value of the source-drain voltage VD with which a constant current source
12
can function is, for example, of about 0.1 V and the threshold voltage Vthn is of about 0.5 V, therefore, the maximum value of the output voltage VO is of about (VDD−0.6) V. In this maximum state, since a source potential of the N-channel FET
10
is much higher than the power supply voltage VSS, the threshold voltage Vthn is higher due to a substrate bias effect, which causes a further fall in the maximum value of the output voltage VO. Since the push-pull amplifier is substantially symmetrical with respect to the middle potential between the power supply potentials VDD and VSS, likewise the minimum value of the output voltage VO is of about (VSS&
Liu Yang
Uasa Tachio
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Shingleton Michael B
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