Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
2002-04-26
2004-02-24
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S269000
Reexamination Certificate
active
06696895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a push-pull amplifier that is provided in an IC or the like that is formed through a CMOS process.
2. Description of the Related Art
FIG. 1
shows a conventional single-input, single-output push-pull amplifier, which may be used as the output stage of an operational amplifier. In such a case, it is desirable that the output of a differential amplifier utilizing n-channel transistors as its inputs be used as the input of the push-pull amplifier.
The push-pull amplifier includes p-channel MOSFETs
21
and
25
(which will be referred to simply as pMOSes
21
and
25
hereinafter); n-channel MOSFETs
22
,
23
,
24
, and
26
(which will be referred to simply as nMOSes
22
,
23
,
24
, and
26
hereinafter); a constant-current source
27
; a phase compensation capacitor
28
; an input terminal IN for receiving an input signal Vin; and an output terminal OUT for outputting an output signal. The input signal Vin is directly supplied to the pMOSes
21
and
25
and to the nMOS
23
. The pMOS
25
and nMOS
26
constitute a push-pull circuit (the output stage).
The pMOS
21
has its gate, source and drain electrodes connected to the input terminal IN, a power supply line VDD and a node ND
21
, respectively. The gate electrode, source electrode and drain electrode will be referred to simply as gate, source and drain, respectively, hereinafter. The nMOS
22
has its gate and drain both connected to the node ND
21
and has its source connected to a ground line VSS. The nMOS
23
has its gate, source and drain connected to the input terminal IN, a node ND
22
and a node ND
23
, respectively. The nMOS
24
has its gate, source and drain connected to the node ND
21
, the ground line VSS and the node ND
22
, respectively. The pMOS
25
has its gate, source and drain connected to the input terminal IN, the power supply line VDD and the output terminal OUT, respectively. The nMOS
26
has its gate, source and drain connected to the node ND
22
, the ground line VSS and the output terminal OUT, respectively. The current source
27
supplies a constant current
127
to the node ND
23
. The capacitor
28
is inserted between the input terminal IN and the output terminal OUT.
In the output stage of the push-pull amplifier shown in
FIG. 1
, the gate of the pMOS
25
directly receives the input signal Vin. Thus, the voltage gain of the gate voltage of the pMOS
25
to the input signal Vin is “1”. Meanwhile, the gate of the nMOS
26
receives the input signal Vin via the pMOS
21
, nMOS
23
and current mirror circuit (the nMOSes
22
and
24
). Thus, the voltage gain of the gate voltage of the nMOS
26
to the input signal Vin is not equal to the voltage gain of the gate voltage of the pMOS
25
.
The voltage gain dVn/dVin of the gate voltage of the nMOS
26
to the input signal Vin will be obtained below. It is now assumed here that the transfer conductance and drain-to-source resistance of the pMOS
21
are gm
2
, and Rds
21
, respectively; the transfer conductance and drain-to-source resistance of the nMOS
22
are gm
22
and Rds
22
, respectively; the transfer conductance and drain-to-source resistance of the nMOS
23
are gm
23
and Rds
23
, respectively; and that the transfer conductance and drain-to-source resistance of the nMOS
24
are gm
24
and Rds
24
, respectively. It is also assumed here that the voltage between the drain of the nMOS
23
and the ground (the voltage at the node ND
22
) is V
23
; the gate-to-source voltage of the nMOS
24
is Vx; the gate-to-source voltage of the nMOS
26
is Vn; and that the internal resistance of the constant-current source
27
is Rds
27
.
The above parameters establish the following equations (1), (2), and (3).
gm21
(
VDD
-
Vin
)
+
VDD
-
Vx
Rds21
=
gm22
*
Vx
+
Vx
Rds22
(
1
)
I27
+
VDD
-
V23
Rds27
=
gm23
(
Vin
-
Vn
)
+
V23
-
Vn
Rds23
(
2
)
I27
+
VDD
-
V23
Rds27
=
gm24
·
Vx
+
Vn
Rds24
(
3
)
From the above equations (1) through (3), the voltage gain dVn/dVin of the gate voltage Vn of the nMOS
26
to the input signal Vin can be expressed by the following equation (4).
ⅆ
Vn
ⅆ
Vin
=
gm23
-
2
gm24
·
-
gm21
1
Rds21
+
1
Rds22
+
gm22
1
Rds23
+
2
Rds24
+
gm23
=
gm23
(
Rds21
+
Rds22
+
gm22
·
Rds21
·
Rds22
)
Rds23
·
Rds24
+
2
gm21
·
gm24
·
Rds21
·
Rds22
·
Rds23
·
Rds24
(
Rds21
+
Rds22
+
gm22
·
Rds21
·
Rds22
)
(
Rds24
+
2
Rds23
+
gm23
·
Rds23
·
Rds24
)
(
4
)
Since gm·Rds is, in general, much greater than 1 (i.e., gm-Rds>>1), the following equation (5) can be figured out by approximating the equation (4).
ⅆ
Vn
ⅆ
Vin
=
2
gm21
·
gm24
gm22
·
gm23
+
1
(
5
)
Moreover, when gm
22
and gm
24
of the nMOSes
22
and
24
, respectively, constituting the current mirror circuit are equal to each other, the voltage gain dVn/dVin can be obtained by the following equation (6).
ⅆ
Vn
ⅆ
Vin
=
2
gm21
gm23
+
1
(
6
)
There may be a case when the gate voltage Vn of the nMOS
26
in the output stage has a value that is slightly greater than the threshold voltage of the nMOS
26
. In such a case, it is necessary to adjust various values so that the voltage difference (Vin−Vn) between the voltage of the input signal (Vin) and the gate voltage of the nMOS
26
(Vn), that is, the gate-to-source voltage of the nMOS
23
, can be large. Thus, it is necessary to make adjustments so that the threshold voltage of the nMOS
23
is higher, or so that the gain coefficient &bgr; of the nMOS
23
is smaller, by elongating the gate length of the nMOS
23
, for example. As a result of this, gm
23
becomes smaller. As shown in the equation (6), when gm
23
becomes smaller, the voltage gain dVn/dVin becomes larger.
Therefore, in the push-pull amplifier shown in
FIG. 1
, the difference between the gain at the pMOS
25
(=1) and the gain at the nMOS
26
(=2·(gm
21
/gm
23
)+1, as shown in the equation (6)) in the output stage with respect to the input signal disadvantageously becomes larger. Consequently, since the gain varies between when the pMOS
25
mainly operates to output a current to the output terminal OUT and when the nMOS
26
mainly operates to input a current from the output terminal OUT, it is difficult to design a push-pull amplifier with a stable operation.
Moreover, for example, since the gain of the path on the n-channel transistor side becomes larger, the gain of the whole operational amplifier, using in its output stage the push-pull amplifier, becomes larger. Consequently, the capacitance value of the phase compensation capacitor
28
disadvantageously becomes larger. In a typical CMOS process, a gate insulator film is utilized to form a capacitor. For this reason, an increase in the capacitance value disadvantageously leads to an increase in the layout area of a push-pull amplifier and hence to an increase in the layout area of an operational amplifier using in its output stage the push-pull amplifier.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a push-pull amplifier with stable operation by reducing the difference between the gains at the respective push-pull transistors in the output stage of the push-pull amplifier with respect to the input signal.
In a form of the push-pull amplifier according to the present invention, a source follower circuit receives, at its gate, an input signal and outputs an input current that corresponds to the input signal. A current transfer circuit receives the input current and maintains constant the sum of the input current and an output current that is to be applied to a first node. A push-pull circuit includes a first transistor that directly receives, at its gate, the input signal and a second transistor having its gate connected to the first node. The push-pull circuit is responsive to the input signal to alternately activate the first and secon
Arent Fox Kintner Plotkin & Kahn
Nguyen Khanh Van
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