Push-back junction isolation semiconductor structure and method

Details Push-back junction isolation semiconductor structure and method Push-back junction isolation semiconductor structure and method

1992-03-04

1993-01-05

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

257550, H01L 2704, H01L 2702

Patent

active

051775875

ABSTRACT:
The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tub, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

REFERENCES:
patent: 3753803 (1973-08-01), Nomura et al.
patent: 3832246 (1974-08-01), Lynch
patent: 4571275 (1986-02-01), Moksvold

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