Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2003-03-10
2004-02-03
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S137000, C257S146000
Reexamination Certificate
active
06686613
ABSTRACT:
BACKGROUND
The present invention relates to a high voltage semiconductor device, and more particularly, to a power device such as an IGBT.
A conventional high voltage vertical power device will be explained below while taking the case of a punch through type IGBT using an epitaxial substrate.
FIG. 1
is a sectional view of a cell area of the conventional punch through type IGBT using the epitaxial substrate.
The epitaxial substrate comprises a positive semiconductor substrate (positive collector layer)
11
and a negative epitaxial layer formed on the semiconductor substrate
11
by an epitaxial growth method. In this example, the epitaxial layer comprises a negative buffer layer
12
and a N type drift layer (active layer)
13
. For example, concentration of positive impurity in the semiconductor substrate
11
is set to about 7.5×10
18
atoms/cm
3
, concentration in the negative impurity in the buffer layer
12
is set to about 2.7×10
17
atoms/cm
3
, and concentration of negative impurity in the drift layer
13
is set to about 1.35×10
14
atoms/cm
3
.
A positive base layer
14
is formed on a surface region of the drift layer
13
. A negative emitter layer
15
and a positive base contact layer
16
are formed in the positive base layer
14
. A negative low resistant layer
17
which is adjacent to the positive base layer
14
is formed in the drift layer
13
.
For example, surface concentration of positive impurity in the positive base layer
14
is set to about 4.0×10
17
atoms/cm
3
, surface concentration of negative impurity in the negative emitter layer
15
is set to about 1.27×10
20
atoms/cm
3
, surface concentration of positive impurity in the positive base contact layer
16
is set to about 2.8×10
19
atoms/cm
3
, and surface concentration of negative impurity in the negative low resistant layer
17
is set to about 5.0×10
15
atoms/cm
3
.
An emitter electrode
18
is formed on the negative emitter layer
15
and the positive base contact layer
16
. The emitter electrode
18
is in contact with the negative emitter layer
15
and the positive base contact layer
16
. A gate electrode
20
is formed on the positive base layer
14
through an insulating film
19
. A collector electrode
21
is formed on a back surface of the semiconductor substrate
11
.
In the conventional power device including the above-described IGBT, an epitaxial substrate is employed. However, manufacturing cost of the epitaxial substrate is high and as a result, a cost of the vertical power device is increased.
In the power device, a so-called life time control is conducted in order to enhance the turn off characteristics. As the life time is shorter, a high speed turn off is possible. Therefore, the life time has been set from a range of 5 to 10 &mgr;s to about 100 ns.
However, as is well known, the turn off characteristics and the on characteristics are in a relation of trade-off. That is, if the turn off characteristics is enhanced, ON voltage becomes higher and on characteristics are deteriorated.
This trade-off relation is generated not only in the above-described punch through type device having the buffer layer, but also in a non-punch through type device having no buffer layer and in a trench gate type device.
SUMMARY
A punch through type power device according to aspect of invention comprises: a first conductive type first base layer having first and second surface areas; a second conductive type collector layer whose thickness is set to 1 &mgr;m or less, and provided in the first surface area; a first conductive type buffer layer between the first base layer and the collector layer; a second conductive type second base layer in the second surface area; a first conductive type emitter layer in the second base layer; a gate insulating film on the second base layer between the emitter layer and the first base layer; and a gate electrode on the gate insulating film.
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S. Dewar, et al. “Soft Punch Through (SPT)—Setting new Standards in 1200V IGBT” Power Conversion, Jun. 2000, Proceedings, pp. 593-600.
T. Laska, et al. “The Field Stop IGBT (FS IGBT)—A New Power Device Concept with a Great Improvement Potential” IEEE International Symposium on Power Semiconductor Devices & ICs 2000, pp. 355-358.
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T. Matsudai, et al. “New 600 V Trench Gate Punch-Through IGBT Concept with Very Thin Wafer and Low Efficiency p-emitter, having an On-state Voltage Drop lower than Diodes” International Power Electronics Conference IPEC—Tokyo 2000, pp. 292-296.
F. Bauer et al., “Design Considerations and Characteristics of Rugged Punchthrough (PT) IGBTs with 4.5kV Blocking Capability”, IEEE, pp. 327-330.
Hattori Hidetaka
Matsudai Tomoko
Nakagawa Akio
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