Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-09-13
2002-02-26
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C327S544000
Reexamination Certificate
active
06351176
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more particularly to integrated circuits having metal-oxide-semiconductor transistors.
BACKGROUND OF THE INVENTION
Metal-oxide-semiconductor (MOS) transistors continue to be a preferred technology for integrated circuits. MOS integrated circuits provide favorable power, speed, density, and noise characteristics. Complementary MOS (CMOS) integrated circuits in particular, provide low power, high noise margins, and large logic swings above and beyond most other common integrated circuit technologies.
Conventional CMOS circuits are well understood in the art. A side cross sectional view of a “bulk” CMOS integrated circuit is set forth in FIG.
1
. The CMOS circuit
100
is formed on a p-type semiconductor substrate
102
. An n-channel MOS (NMOS) transistor
104
is formed in the p-type substrate
102
, and includes an NMOS gate
106
, an NMOS source
108
and an NMOS drain
110
. The NMOS source and drain (
108
and
110
) are shown to be formed from n-type diffusions within the p-type substrate
102
. The circuit
100
further includes an n-type well
112
formed within the p-type substrate
102
. In a similar fashion to the NMOS transistor
104
, a p-channel MOS (PMOS) transistor
114
is formed within the n-well
112
. The PMOS transistor
114
has a PMOS gate
116
, a PMOS source
118
and a PMOS drain
120
. The PMOS source and drain (
118
and
120
) are formed by p-type diffusions within the n-type well
112
.
The substrate in which each transistor is formed is considered the “body” of the transistor. In particular, the p-type substrate
102
forms the body for NMOS transistor
104
, and the n-type well
112
forms the body for PMOS transistor
114
. As shown in
FIG. 1
, in a conventional CMOS configuration the p-type substrate (the body of the NMOS transistor
104
) is coupled to the low power supply voltage VSS by a first supply substrate contact
122
, and the n-type well (the body of the PMOS transistor
114
) is coupled to the high power supply voltage VDD by a second supply substrate contact
124
.
As is well understood in the art, when the circuit
100
is in operation, provided there is a sufficient potential across the NMOS source
108
and NMOS drain
110
, when the gate-to-source voltage applied at the NMOS gate
106
exceeds an n-channel transistor threshold voltage (Vtn), a current path will be formed between the NMOS source
108
and NMOS drain
110
. In this manner, the NMOS transistor
104
is switched on. When the gate-to-source voltage is less than Vtn, the NMOS transistor
104
is switched off. Similarly, provided there is a sufficient potential between PMOS source
118
and PMOS drain
120
, when the gate-to-source voltage applied at PMOS gate
116
has an absolute value that is less than the absolute value of a p-channel threshold voltage (|Vtp|), PMOS transistor
114
is switched on. When the magnitude of the gate-to-source voltage is less than |Vtp|, PMOS transistor
114
is switched off.
The amount of current drawn by a MOS transistor (I
DS
) is a function of Vgs−Vt, where Vgs is the gate-to-source voltage and Vt is the threshold voltage of the transistor. Thus, the value of Vt will affect the amount of current the transistor can source or sink (the “drive” current). Transistors with a lower threshold voltage will draw more current, and thus provide a faster switching action. Transistors with a higher threshold voltage will draw less current and result in a slower switching action. The threshold voltage of a MOS transistor also effects the leakage current of a transistor. When a transistor's Vgs voltage is less than the transistor's threshold voltage (the transistor is “off”), a leakage current will still be drawn by the transistors. The leakage current is also dependent upon the Vt value. A lower Vt value will result in higher leakage currents, while a higher Vt value will result in lower leakage currents. It is the above described switching of the transistors within the MOS circuit
100
that determines how fast the circuit
100
can operate. The particular circuit
100
of
FIG. 1
illustrates a CMOS inverter. The inverter is set forth in a schematic diagram in
FIG. 2
, and identified by the general reference character
200
. The PMOS transistor is shown as P
200
and the NMOS transistor is shown as N
200
. The inverter
200
receives an input signal (IN) at an input node
202
, and provides an output signal (OUT) at an output node
204
that is the inverse of the IN signal. When the IN signal exceeds the Vtn of transistor N
200
, the OUT signal is driven low (to VSS). When the IN signal is lower than VDD by the Vtp of transistor P
200
, the OUT signal is driven high (to VDD). Thus, the maximum speed at which the inverter
200
can operate depends, in part, upon the threshold voltages of its respective transistors.
It is known in the prior art to modulate the Vt of MOS transistors by altering the threshold voltage of the transistors. Such Vt modulation schemes have involved semiconductor-devices that have active modes, in which switching of transistors is likely to occur, and standby modes, in which switching of transistors is not likely to occur. In the standby mode, the Vt is raised, to limit leakage when the transistor is turned off. In the active modes, the Vt is lowered. Furthermore, within such Vt modulation schemes, the range to which the Vt values can be altered is limited, in order to prevent the forward biasing of the body-to-source pn junction. Maintaining body-to-source pn junction in the forward biased state can draw unacceptably large amounts of current. A drawback to driving body voltages in order to lower Vts throughout an active mode, is that maintaining transistor bodies at the low Vt inducing voltage for such a long period of time will draw considerable leakage current, resulting in increased active mode power consumption.
One example of a prior art scheme for modulating transistor Vts, is to couple the body of a transistor to its drain voltage according to a preceding input signal. When the input signal is active, indicating possible transistor switching actions, the body of the transistors will be coupled to the transistor drains, altering the body voltages and lowering the Vts of the transistors.
Referring once again to
FIG. 1
, as noted previously, the p-type substrate
102
is coupled to the low power supply voltage VSS (by first supply substrate contact
122
), while the n-type well
112
is coupled to the high power supply voltage VDD (by second supply substrate contact
124
). This arrangement helps to maintain the n-well
112
and p-type substrate
102
at a reverse bias state with respect to one another, and enabling NMOS and PMOS transistors to operate within the same semiconductor substrate.
“A 1-V 46-ns 16-Mb SOI DRAM with Body Control Technique” appearing in
IEEE Journal of Solid-State Circuits
, Vol. 32, No. 11, pages 1712-1719, and dated November 1997, by Shimomura et al. sets forth a silicon-on-insulator (SOI) dynamic random access memory (DRAM). The SOI DRAM includes SOI transistor circuits in which the transistor Vts are modulated by coupling the bodies of the transistor to “medium-level” voltage in order to lower the transistor Vts. The medium-level voltage is a voltage having a level between the power supply voltages, and is used to prevent forward biasing of the body-source/drain junctions. Transistors are returned to a higher Vt level by coupling the bodies to the power supply voltages.
Shimomura et al. in particular, illustrates a sense amplifier circuit having SOI transistors with bodies that are connected to the “medium-level” voltage at about the same time the sense amplifier is turned on. If reference is made to
FIG. 5
of Shimomura et al., it is shown that in the disclosed sense amplifier scheme, the bodies of the cross-coupled transistors (M
1
-M
4
) are lowered during an initial “sense” period (when the data value on the bit lines is determined). Subsequently, durin
Brady III W. James
Hernandez Pedro P.
Kim Jung Ho
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