Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-12-15
2002-08-13
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000, C327S208000
Reexamination Certificate
active
06433601
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of electronic circuit design, and in particular to a pulse-triggered D-Flip-Flop (P-DFF) that utilizes a cascode voltage switch to achieve minimal set-up time and propagation delay, while also consuming minimal power.
2. Description of Related Art
A Data-Flip-Flop (DFF) is configured to “read” a data input at a particular point in each clock cycle. The output of the DFF provides the value that was read, independent of subsequent changes, or noise, on the data input, until the next data value is read. The data input must be stable while it is being read into the DFF, else the read value may be indeterminable. Ideally, the reading of the data input occurs instantaneously, so that the sensitivity of the DFF to changes on the data input is minimized. Also ideally, the instantaneous read occurs at exactly the same point within each clock cycle.
Pulse-triggered latches and flip-flops are commonly used in the art to approximate the ideal performance of a DFF as closely as possible [1]. In a pulse-triggered latch, a pulse generator provides a narrow pulse at each rising or falling (active) edge of a clock. While the pulse is asserted, the signal on a data input line is communicated to the output of the latch. While the pulse is not asserted, the output of the latch remains unchanged. In order to maximize the stability of the output, and to reduce the stability requirements on the data input, the width of the asserted pulse is kept as narrow as possible.
1
. Vladimir Stojanovic and Vojin G. Oklobdzija, “Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems”, IEEE Journal of Solid-State Circuits, Vol 34, No. 4, April 1999, pp 536-548, and incorporated by reference herein.
The performance of a DFF is assessed in terms of its cycle delay, or “sequencing overhead”, and its power consumption. The sequencing overhead is defined herein as the minimum time required to read the data into the device and to produce a stable output corresponding to this data input. This includes any set-up requirements imposed on the data input to assure a reliable read of the data value, plus the time required to propagate the data input to the output of the device. This sequencing overhead corresponds, inversely, to the maximum speed that a serial string of DFFs can be reliably operated. If the DFF includes additional internal logic, such as scan logic that is used for testing the device, the sequencing overhead includes the impact, if any, that the additional internal logic imposes on the propagation of the data input to the output of the DFF during normal (i.e. performance) operation. The power consumption of a DFF typically depends upon the energy required to change the state of the elements within the DFF, and hence, is typically dependent upon pattern of data values read by the DFF. Generally, the power consumption of a DFF is estimated based upon an assumed random data input pattern to the DFF.
FIGS. 1-3
illustrate example prior art pulsed-D-Flip-Flops. In
FIG. 1
, an example “hybrid-latch” flip-flop (HLFF) is illustrated [2, 3] that achieves a high speed performance via a pre-charging of the internal nodes
101
of the flip-flop to avoid the delay associated with changing the value of the internal nodes to the pre-charged value when the device is clocked to read in the data. When the clock (CLK) signal is low, the p-channel device
121
conducts, thereby precharging the internal node
101
to a high state. This internal high state has no effect on the output Q, because the low clock signal also places the n-channel device
132
into a non-conducting state, thereby precluding a discharge of the voltage at Q. Also, while the clock signal is low, the inverting delay logic
110
places the n-channel devices
124
and
134
into a conducting state.
2
. ibid,
FIG. 17.
3
. Draper et al., “Circuit Techniques in a 266-MHz MMX-enabled processor”, IEEE Journal of Solid-State Circuits, Vol 32, November 1997, pp 1650-1664, and incorporated by reference herein. See FIG. 10.
When the clock signal goes high, the p-channel device
121
is placed in a non-conducting state, and device
122
in a conducting state. Because, initially, devices
122
and
124
are in a conducting state, the value of the data signal at the gate of n-channel device
123
determines the state of the internal node
101
. If the data signal is low, the internal node
101
remains at a high state; if the data signal is high, the internal node
101
is discharged through the serial path of devices
122
,
123
, and
124
to a low state. Also when the clock signal initially goes high, devices
132
and
134
are in a conducting state, and the inversion of the state of the internal node
101
is communicated to the output Q.
The asserted clock signal propagates through the inverted delay logic
110
, and after approximately three gate-time delays, the high value at the clock produces a low value at the gates of devices
124
and
134
, placing each of them in a non-conducting state. In this non-conducting state, neither the internal state
101
nor the output Q can be discharged to a low state. Because the internal state
101
cannot be discharged to a low state, the state of the p-channel device
131
cannot change. If the internal state
101
had been low, device
131
would have been conducting, and the output Q would be in a high state, and will remain in this high state because the device
134
is in a non-conducting state. If the internal state
101
had been high, device
131
would have been non-conducting, and the output Q would have been in a low state (via
132
,
133
,
134
when the clock initially goes high). The internal state
101
will remain in this high state because device
124
is non-conducting.
When the clock again goes low, the internal state
101
is again precharged to a high state. This precharging has no effect on the output Q, because the device
132
is non-conducting when the clock signal is low and cannot discharge the output Q if it is currently in the high state. The precharging of the internal node
101
places device
131
into a non-conducting state, and thus cannot charge the output Q if it is currently in the low state.
The internal state
101
is also precharged if the data input value is in a low state, via the p-channel device
141
, regardless of the state of the clock. This precharging cannot affect the output Q unless both devices
132
and
134
are conducting, which occurs only during the intended time for the data input to be propagated to the output Q.
The cross-coupled inverters
140
provide a complementary output Qn, and provide an additional margin of stability to the output Q during transitions in the above described process, or during long periods of clock inactivity.
As described above, the state of the internal node is dependent upon the data signal only during the period that both n-channel devices
122
and
124
are conducting. This time of mutual conduction is determined by the delay block
110
. The delay time of the delay block
110
is set to be as short as possible, while still assuring that the value on the data line will be propagated to the output Q. Because the internal node
101
is precharge to a high state, the delay for propagating a data low state is merely the delay of the n-channel device
132
for discharging the output Q to a low state, if it is not already in the low state. The delay for propagating a data high state is the delay of the n-channel device
122
for discharging the internal node
101
, plus the delay of the p-channel device
131
for charging the output node Q to a high state, if it is not already in the high state. Note, however, that the delay of the device
110
need only be long enough for the n-channel device
122
to discharge the internal node
101
via the data-controlled device
123
, or for the n-channel device
132
to discharge the output Q via the internal-node-controlled device
133
.
Koninklijke Philips Electronics , N.V.
Le Dinh T.
Tsiang Harold
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