Pulsed clock signal transfer circuits with dynamic latching

Details Pulsed clock signal transfer circuits with dynamic latching Pulsed clock signal transfer circuits with dynamic latching

1999-12-20

2003-12-23

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S201000

Reexamination Certificate

active

06667645

ABSTRACT:

FIELD
The present invention relates, generally, to the field of signal transfer clocking circuits and, more particularly, to logic signal transfer circuits employing phase/pulse clocking methodology, including, although not limited thereto, pulsed clock gated logic circuits in processors (e.g., microprocessors).
BACKGROUND
Recently, there has been realized significant achievements in scaling down of the sizes so of active elements in semiconductor integrated circuits (ICs), in the level of integration of an IC chip and, also, in the scaling down of the supply voltages of IC chips, as well as in the voltage/current levels assigned to logic levels of integrated circuits. Such developments have been particularly noticeable in CMOS (Complementary Metal-Oxide Semiconductor) technology, which has led to the development of single-chip processors (i.e., microprocessors) with ever increasing clocking speeds. However, as the channel length Leff (effective channel length) is lowered below 0.2 microns, it becomes more and more difficult to reduce gate delay, due to mobility reduction and series resistance limitations. Therefore, with increasing clock frequency in microprocessors, the clock inaccuracy becomes a significant percentage of the clock period. It is critical, therefore, that we account for the clock inaccuracy in connection with the transfer of data (e.g., logic signals) in the die (processor chip). For example, you may have a global clock tree distribution in which similar generated clocks may not arrive at the end of the distribution clock tree at exactly the same time for a number of reasons, including that the component elements are not perfectly matched throughout the chip. There may be faster components at one location of the chip than at another, or you may have a drop in the power supply at one location of the chip and not at another, which would cause a difference in delay in signal propagation.
Basically, the clock inaccuracy consists of two components, namely, clock skew and clock jitter. Clock jitter can be noticed when monitored on an oscilloscope in which the thickness of the rising edges (bands) represents the extent of excursion of the clock edges from the nominal timings and is referred to as the peak-to-peak jitter. There is also clock skew which represents the spacial separation effect of the clock inaccuracy. An example of this is shown in
FIGS. 19A and 19B
in which two clocks, namely, ClkA and ClkB, are generated by the same source and are designed for equal delay T
0
. However, the two paths which include equal numbers of series-connected logic inverters (e.g., CMOS inverters) are disposed over two different locations on the die. For example, assume that path B is laid out next to large bus drivers (with a high activity factor) in which case the supply voltage may be lower than that for the devices in path A, which neighbors only small gates with very low activity factor. Further, assume that the channel lengths of the MOSFETs (Metal-Oxide Semiconductor Field-Effect Transistors) in path B came out to be longer than nominal because of some optical distortion from defects in the lens, while devices in path A were unaffected. Obviously, the delay T
B
through path B will be longer than the designed nominal delay T
0
, while the delay T
A
, through path A, will be shorter than delay T
0
. The skew between the two clocks is then the difference T
B
−T
A
, as is clearly seen from the timing diagram in FIG.
19
B. In general, skew can also be between two paths of designed unequal delays. Using CMOS technology as an example, there are a number of reasons contributing to clock skew, including but not limited to (1) threshold voltage variation of MOS transistors across the die; (2) interlayer dielectric thickness variation; (3) design errors; (4) supply voltage variation across the die; (5) temperature difference across the die; (6) signal coupling to neighboring lines; and (7) variation in the effective channel length of MOS devices across the die.
With regard to the phenomena of clock skews, the potential for realizing a race condition resulting from min-delay (minimum delay) becomes even more pronounced with attempts at achieving higher and higher processor clocking speeds. For example, assume you have a generator block including a first logic circuit with plural signal paths and a receiver block including a second logic circuit and that each of those blocks is controlled by clock signals generated by different local clock generators. Assume also the presence of clock skew as a result of any one or more of the number of reasons discussed above. Thus, if the local clock generators associated with the first logic circuit generate clock signals faster than that of the local clock generators associated with the second logic circuit, in the receiving block, the signals may arrive at their destination faster than desirable and potentially may race through the receiving block. This can cause inaccurate operation (e.g., glitches or spurous transitions, etc.) of the individual logic circuits and, therefore, of the overall circuitry in the die. In fact, such, min-delay race conditions can adversely affect the development of higher and higher processor clocking speeds.
SUMMARY
A signal transfer clocking circuit has a first stage including a first latch and a first, non-clocking circuit in series therewith. The first latch has a data input and is opened in response to a first level of a pulse clock signal applied thereto to effect transfer of incoming data through the first stage in a first phase of operation of the signal transfer clocking circuit. The signal transfer clocking circuit further has a second stage including a second, dynamic latch and at least a second circuit in series therewith. The dynamic latch has a data input, coupled to an output of the first circuit, and is opened in response to a second level of a same or different pulse clock signal applied thereto as that applied to the first latch to effect a transfer of data generated by the first stage, through the second stage, to at least one succeeding circuit in a second, successive phase of operation of the signal transfer clocking circuit. The succeeding circuit is opened and closed by a clock signal having phase and frequency characteristics linked to that applied to the dynamic latch. (An opened latch refers to a latch in an ON-state, namely, a conducting state; a closed latch refers to a latch in an OFF-state, namely, a non-conducting state.)


REFERENCES:
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5300831 (1994-04-01), Pham et al.
patent: 5457698 (1995-10-01), Segawa et al.
patent: 5553276 (1996-09-01), Dean
patent: 5619157 (1997-04-01), Kumata et al.

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