Pulsed bootstrapping output buffer and associated method

Details Pulsed bootstrapping output buffer and associated method Pulsed bootstrapping output buffer and associated method

1991-01-16

1992-06-23

LaRoche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307451, H03K 1912, H03K 1996

Patent

active

051245850

ABSTRACT:
An output buffer circuit is provided for use with a first external voltage which provides voltage at a first level, the output buffer circuit comprising: an output terminal; a second voltage supply for providing voltage at a second level less than the first level; an n-channel pull-up transistor including a drain coupled to the first voltage supply and including a source coupled to the output terminal; a p-channel pull-up transistor including a drain coupled to the output terminal and a source coupled to the second voltage supply; an n-channel pull-down transistor including a drain coupled to the output terminal; a bootstrapping turn-on circuit for raising a gate of the n-channel pull-up transistor to a raised voltage level which is above the first voltage level such that the n-channel pull-up transistor becomes turned on; a turn-off circuit for turning off the n-channel pull-up transistor when the output terminal has been substantially pulled up to the second voltage level; and a turn-on circuit for turning on the p-channel pull-up transistor when the output voltage at the output terminal has been substantially pulled up to the second level.

REFERENCES:
patent: 4395644 (1983-07-01), Misaizu
patent: 4508978 (1985-04-01), Reddy
patent: 4611134 (1986-09-01), Ando
patent: 4617476 (1986-10-01), Dalrymple
patent: 4633105 (1986-12-01), Tsujimoto
patent: 4914323 (1990-04-01), Shibata

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