Pulse wordline control circuit and method for a computer memory

Details Pulse wordline control circuit and method for a computer memory Pulse wordline control circuit and method for a computer memory

1998-08-20

1999-09-28

Phan, Trong

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518907, 36518909, G11C 800, G11C 1604

Patent

active

059599340

ABSTRACT:
A PWL control circuit and method is provided for use on a memory device to control the high/low logic state of the wordlines connected to the memory cell array of the memory device during access operation. The memory device can be a DRAM (dynamic random-access memory) device or an SRAM (static random-access memory device). The PWL control circuit and method utilizes a feedback signal from the sense amplifier to control the high/low logic state of the wordlines of the memory device. This feature can help eliminate the problem of an early deactivation of the currently activated wordlines during access operation that would otherwise occur when using the RC delay circuit in the prior art. Therefore, even if process parameters of the memory device are changed, the reliable sensing of the data from the memory cells is not affected.

REFERENCES:
patent: 5287326 (1994-02-01), Hirata
patent: 5896324 (1999-04-01), Jang et al.

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