Electric power conversion systems – Current conversion – With condition responsive means to control the output...
Reexamination Certificate
2001-07-30
2003-06-10
Riley, Shawn (Department: 2838)
Electric power conversion systems
Current conversion
With condition responsive means to control the output...
C363S127000
Reexamination Certificate
active
06577517
ABSTRACT:
TECHNICAL FIELD
This invention relates to power supplies for electronic equipment and, in particular, to control circuits for series resonant AC/DC converters for producing controlled DC output voltages with ultra fast transient response from a high frequency AC bus for computing and network equipment such as personal computers, servers, and high speed routers.
BACKGROUND OF THE INVENTION
FIG. 1
shows a circuit diagram of a synchronous rectifier section of
100
of one embodiment of a pulse width modulated high frequency AC to DC converter described in Applicants' co-pending U.S. patent application No. 09/464,950, filed on Feb. 1, 2000. The converter
100
includes a transformer
106
with a primary winding
106
A and a center tapped secondary winding
106
B. A series resonant circuit
104
, that includes a first capacitor
104
A and an inductor
104
B, is connected in series with the primary winding
106
A. An AC input voltage
102
(V
s
) is applied across the series resonant circuit
104
and primary winding
106
A. A first switch, which is preferably a FET
108
(field effect transistor) having a drain
108
C, is connected to a first terminal of the secondary winding
106
B. A source
108
B of the FET
108
is connected to a reference node
130
. A first gating signal
110
(Vgs
1
) is applied across a gate
108
A of the FET
108
and the reference node
130
. A first diode
111
has an anode connected to the source
108
B and a cathode connected to the drain
108
C of the FET
108
. A first capacitor
112
is connected across the source
108
B and drain
108
C of the FET
108
. Similarly, a second switch , which is preferably also a FET, has a drain
116
C connected to a second terminal of the secondary winding
106
B. A source
116
B of the FET
116
is connected to the reference node
130
. A second gating signal
122
(Vgs
2
) is applied across a gate
116
A of the FET
116
and the reference node
130
. A second diode
118
has an anode connected to the source
116
B and a cathode connected to the drain
116
C of the FET
116
. A second capacitor
120
is connected across the source
116
B and drain
116
C of the FET
116
. A third capacitor
124
is connected from a center tap terminal of the transformer
106
to the reference node
130
. A DC output F voltage
128
across the third capacitor
124
is connected to a load
126
(shown in dashed lines).
FIG. 2
illustrates the required gating signals
200
for controlling the output of the converter
100
of FIG.
1
. The AC input voltage
102
(
FIG. 1
) is a sine wave
202
. The first gating signal
110
(
FIG. 1
) is a first rectangular wave
204
and the second gating signal
122
(
FIG. 1
) is a second rectangular wave
206
. The following is required for successful generation of the gating signals
204
,
206
of FIG.
2
.
1. The gating signals
204
,
206
should be frequency synchronized with the AC input voltage
102
.
2. The gating signals
204
,
206
should be phase synchronized with the AC input voltage
102
.
3. A full pulse width of the gating signals
204
,
206
should be about 180° in duration.
4. A minimum pulse width of the gating signals
204
,
206
should be about 0° in duration.
5. The gating signals
204
,
206
should not cause cross conduction of the FETs
108
,
116
.
6. The gating signals
204
,
206
should supply high currents to the gates
108
A,
116
A of the FETs
108
,
116
at a voltage higher than a gate threshold voltage of the FETs
108
,
116
.
There are a number of off-the-shelf Pulse Width Modulation (PWM) integrated circuits (IC) available, which can provide dual output signals that can be synchronized in frequency but cannot be synchronized in phase. One way of implementing a control circuit for the generation of the gate signals using an off-the-shelf PWM, such as UC 2823 from Texas Instruments, is shown in FIG.
3
. The control circuit
300
consists of the following functional blocks: an auxiliary transformer
302
for isolating the AC input voltage
102
from control circuits; a zero crossing detector circuit
306
for the high frequency voltage/current; a synchronization circuit
310
for phase and frequency synchronization; a PWM
320
for controlling pulse generation; a first and second phase synchronization circuit
326
,
334
; and a first and second driver circuit
330
,
338
. First and second outputs (signals A and B) of the auxiliary transformer
302
are connected at
304
to a first and second input of the zero crossing detector
306
. First and second outputs (signals A
1
and B
1
) of the zero crossing detector
306
are connected at
308
to a first and second input of the synchronization circuit
310
. A first output (clock) of the synchronization circuit
310
is connected at
312
to a first input of the PWM
320
. A second input of the PWM is connected at
324
to a feedback signal. An output (P
PWM
) of the PWM
320
is connected at
322
to a first input of the first and second phase synchronization circuits
326
,
334
. A second and third output (signals A′ and B′) of the synchronization circuit
310
are connected at
314
and
316
respectively to second inputs of the first and second phase synchronization circuits
326
,
334
. An output (PA) of the first phase synchronization circuit
326
is connected at
328
to an input of the first driver circuit
330
. An output of the first driver circuit
330
provides the first gating signal
110
(V
gs1
). An output (PB) of the second phase synchronization circuit
334
is connected at
336
to an input of the second driver circuit
338
. An output of the first driver circuit
338
provides the second gating signal
122
(V
gs2
). For convenience the PWM
320
; first and second phase synchronization circuits
326
,
334
; and first and second driver circuits
330
,
338
will be referred to collectively as an output circuit
340
.
Due to a delay in detecting zero voltage crossings, generation of the synchronizing clock pulse, inherent delay in the PWM
320
, phase synchronization and internal delay of the drivers
330
,
338
, the gating signals
110
,
122
generated for FETs
108
,
116
corresponding to positive and negative half cycles respectively of the AC input voltage
102
, are also delayed.
An illustration of the signals
400
generated by the PWM IC shown in
FIG. 3
is illustrated in FIG.
4
. The auxiliary transformer
302
generates two complementary voltage signals A
402
and B
404
at its output. The zero crossing detector circuit
306
generates signals A′
406
and B′
408
. Signals A′
406
and B′
408
correspond to the positive half-cycles of signals A
402
and B
404
respectively. The synchronization clock generator
310
generates a clock signal
410
that is twice the frequency of input signals A
402
and B
404
. The clock signal
410
is used to synchronize the PWM
320
at twice the frequency of the AC input voltage
102
. Based on the feedback signal
324
, PWM
320
generates signal
412
(P
PWM
), which is delayed with respect to the clock signal
410
due to the internal delay t
dPWM
in the PWM
320
. The first and second phase circuits
326
,
334
generate signals P
A
414
and P
B
416
which are in phase and frequency with the positive half-cycles of signals A
402
and B
404
respectively. Signals P
A
414
and P
B
416
are used to drive the first driver
330
(
FIG. 3
) and second driver
338
respectively to produce gating signals V
gs1
418
and V
gs2
420
. The internal delays t
dDriver
of these external drivers further delays the gating signals V
gs1
418
and V
gs2
420
with respect to the clock signal
410
, and consequently with respect to the zero crossings of the input signals A
402
and B
404
.
A total typical delay of the circuit is in the order of 125 ns to 150 ns. At frequencies of 1 MHz and higher, this delay is a significant proportion of the switching cycle. This delay in the gating signals
418
,
420
causes two problems, namely, it reduces the effective duty cycle for the conduction of the FETs
108
,
116
, and it ca
Jain Praveen Kumar
Zhang Haibo
ChipPower. com, Inc.
Renault Ogilvy
Riley Shawn
Wood Max R.
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