Pulse or digital communications – Pulse width modulation
Reexamination Certificate
2000-06-28
2002-07-16
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Pulse width modulation
C332S109000, C370S212000, C327S172000
Reexamination Certificate
active
06421382
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a pulse signal generator, and in particular to an apparatus and method for generating a pulse width modulation (PWM) signal according to given data.
2. Description of the Related Art
In general, a PWM signal generator employs a phase-locked loop circuit that generates a rectangular clock signal from a system clock signal and a PWM controller for producing a PWM signal from the rectangular clock signal and a modulating signal. This type of PWM signal generator is disclosed in, for example, Japanese Patent Application Unexamined Publication No. 10-209829.
As another approach, there has been proposed a PWM generator having a free-run counter, master and slave compare registers, a transfer controller, and an output circuit (Japanese Patent Application Unexamined Publication No. 10-268902). More specifically, the free-run counter generates a overflow signal when its counted value reaches a predetermined value. A microprocessor or CPU writes a set value to the master compare register through a data bus. The transfer controller allows the set value to be transferred from the master compare register to the slave compare register and inhibits the transfer of the set value in response to an the overflow signal. A comparator compares the counted value of the free-run counter and the set value transferred into the slave compare register and generates a coincident signal when the counted value is coincident with the set value. The output circuit generates a PWM signal in response to the overflow signal and the coincident signal.
In the case where both cycle value and duty value of a PWM signal are controlled, however, it is necessary for the CPU to manage the write timing of cycle and duty set values so as to prevent the PWM signal from being generated at undesired timing and in undesired combinations of cycle and duty values. In this case, another counter for controlling the write timing is needed, resulting in increased amount of hardware.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a PWM signal generating apparatus and method allowing designed cycle and duty of a PWM signal to be produced with reliability and without increasing in the amount of hardware.
According to the present invention, an apparatus for generating a pulse width modulation (PWM) signal depending on a sequence of combinations of cycle set value and duty set value which are received from a controller, includes: a first cycle setting memory for storing the cycle set value which is written according to a cycle write control signal; a second cycle setting memory for storing a current cycle set value which is transferred from the first cycle setting memory according to a transfer permit signal; a first duty setting memory for storing the duty set value which is written according to a duty write control signal; a second duty setting memory for storing a current duty set value which is transferred from the first duty setting memory according to the transfer permit signal; a timer for counting according to a predetermined clock signal to produce a counted value; a cycle comparator for comparing the counted value to the current cycle set value to produce a cycle coincidence signal when the counted value reaches the current cycle set value, wherein the cycle coincidence signal causes the timer to be reset to zero; a duty comparator for comparing the counted value to the current duty set value to produce a duty coincidence signal when the counted value reaches the current duty set value; and an output section for setting the PWM signal when the cycle coincidence signal is produced and resetting the PWM signal when the duty coincidence signal is produced.
When at least one of cycle and duty of the PWM signal is changed in a following cycle, at least corresponding one of the cycle write control signal and the duty write control signal may be received from the controller until the cycle coincidence signal is produced.
A transfer controller is preferably provided which produces the transfer permit signal based on the cycle coincidence signal, the cycle write control signal, the duty write control signal, and an operation status of the timer. The transfer controller may produce the transfer permit signal when the cycle coincidence signal is produced in an interval after the duty write control signal has been produced and before the cycle write control signal is produced. In other words, the transfer controller sets a write history flag when the cycle write control signal is produced and resets the write history flag when the duty write control signal is produced, wherein the transfer permit signal is produced when the cycle coincidence signal is produced and the write history flag is in reset status, and the transfer permit signal is not produced when the cycle coincidence signal is produced and the write history flag is in set status.
A transfer controller may be provided which produces the transfer permit signal when a transfer request signal is received from the controller.
According to the present invention, a method for generating a pulse width modulation (PWM) signal depending on a sequence of combinations of cycle set value and duty set value which are received from a controller, includes the steps of: a) storing the cycle set value which is written according to a cycle write control signal, into a first cycle setting memory; b) storing a current cycle set value which is transferred from the first cycle setting memory according to a transfer permit signal, into a second cycle setting memory; c) storing the duty set value which is written according to a duty write control signal, into a first duty setting memory; d) storing a current duty set value which is transferred from the first duty setting memory according to the transfer permit signal, into a second duty setting memory; e) counting according to a predetermined clock signal to produce a counted value; f) comparing the counted value to the current cycle set value to produce a cycle coincidence signal when the counted value reaches the current cycle set value, wherein the cycle coincidence signal causes the counted value to be reset to zero; g) comparing the counted value to the current duty set value to produce a duty coincidence signal when the counted value reaches the current duty set value; and h) setting the PWM signal when the cycle coincidence signal is produced and resetting the PWM signal when the duty coincidence signal is produced.
REFERENCES:
patent: 5177373 (1993-01-01), Nakamura
patent: 5298871 (1994-03-01), Shimohara
patent: 5404116 (1995-04-01), Ichihara
patent: 5963107 (1999-10-01), Nagano et al.
patent: 10-209829 (1998-08-01), None
patent: 10-268902 (1998-10-01), None
Ghebretinsae Temesghen
NEC Corporation
Sughrue & Mion, PLLC
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