Pulse or digital communications – Receivers
Reexamination Certificate
2008-06-09
2011-11-29
Lam, Kenneth (Department: 2611)
Pulse or digital communications
Receivers
C375S354000, C375S340000, C375S343000, C375S346000, C375S344000
Reexamination Certificate
active
08068559
ABSTRACT:
The present disclosure generally relates to pulse width modulation (PWM) clock and data receivers and methods for recovering data and timing information from received signals. A PWM clock and data receiver in one exemplary embodiment of the present disclosure has comparators for detecting pulses of a received data signal. The PWM clock and data receiver provides fixed frequency, variable duty cycle control signals that are used to control the biasing of the comparators to establish data decision levels for clock and data recovery. At times, the output of at least one comparator is used to perform peak detection, and the receiver controls the duty cycles of the control signals based on such peak detection in an effort to optimize the clock and data recovery process.
REFERENCES:
patent: 4315220 (1982-02-01), Findeisen
patent: 4373140 (1983-02-01), Chin
patent: 4620444 (1986-11-01), Young
patent: 4622586 (1986-11-01), Megeid
patent: 4667333 (1987-05-01), Butcher
patent: 4847870 (1989-07-01), Butcher
patent: 5940442 (1999-08-01), Wong et al.
patent: 6137850 (2000-10-01), Miller
patent: 6438178 (2002-08-01), Lysdal et al.
patent: 6472861 (2002-10-01), Chen et al.
patent: 6751745 (2004-06-01), Yoshimura et al.
patent: 6760389 (2004-07-01), Mukherjee et al.
patent: 7091793 (2006-08-01), Bardsley et al.
patent: 7120216 (2006-10-01), Shirota et al.
patent: 7123046 (2006-10-01), Keeth
patent: 7269347 (2007-09-01), Matricardi et al.
patent: 2002/0027688 (2002-03-01), Stephenson
patent: 2003/0031282 (2003-02-01), McCormack et al.
patent: 2006/0077850 (2006-04-01), Umetani
patent: 2006/0091925 (2006-05-01), Desai et al.
patent: 2009/0289683 (2009-11-01), Wong
Dallas Maxim, “DS21348/DS21Q348 3.3V E1/T1/J1 Line Interface,” Jan. 12, 2006, pp. 1-9, and 49.
Cirrus Logic, “CS61584A Dual T1/E1 Line Interface,” Sep. 2005, pp. 1, and 18-19.
ADTRAN Inc.
Holland Jon E.
Lam Kenneth
Lanier Ford Shaver & Payne P.C.
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