Electric power conversion systems – Current conversion – With means to introduce or eliminate frequency components
Reexamination Certificate
2002-09-16
2004-08-10
Nguyen, Matthew V. (Department: 2838)
Electric power conversion systems
Current conversion
With means to introduce or eliminate frequency components
Reexamination Certificate
active
06775158
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention relates generally to inverters. More particularly, the invention relates to a pulse width modulation controller for inverters.
BACKGROUND INFORMATION
Inverter drivers are commonly used to control AC induction motors. Inverters create variable AC waveforms from a direct current (DC) source to drive AC induction motors. The Pulse Width Modulation (“PWM”) control technique is the standard technique used to create the desired frequency and voltage of the AC waveforms.
FIG. 1
is a block diagram of a prior art controller for a DC to AC inverter using the standard PWM technique. As shown in
FIG. 1
, a signal generator
110
is electrically coupled to a controller unit
100
. The controller unit
100
in turn drives the inverter
190
. The signal generator
110
provides the controller unit
100
with two sources of signals, a sinusoidal signal (“PWMDATA”)
101
and a high frequency triangular carrier signal (“CARRIER CNT”)
102
, which are used to shape the amplitude and frequency of the desired AC waveform.
Controller unit
100
includes a PWM Pulse Generator
113
and a top-bottom output controller
118
. Included in the PWM Pulse Generator
113
is a comparator
114
which compares the PWMDATA signal
101
with the CARRIER CNT signal
102
and generates a resulting output variable square wave signal PWM OUT
119
. When the PWMDATA
101
is higher in amplitude than the CARRIER CNT
102
, the amplitude of the PWM OUT
119
will be high; similarly, when the PWMDATA
101
is lower in amplitude than the CARRIER CNT
102
, the PWM OUT
119
will have an amplitude that is low.
In using PWM technique, two PWM signals are required to synthesize the two polarities of the AC waveform. Thus, the PWM OUT
119
signal and its complement signal (/PWM OUT
120
) are separately fed through two separate AND gates
126
,
128
within the top bottom output controller
118
. Additionally, the PWM OUT
119
will pass through a first delay
122
as PWM DLY before reaching one of two inputs to the first AND gate
126
while the same PWM OUT
119
signal is passed through to the other input of the first AND gate
126
. The resulting output of AND gate
126
is signal PWM TOP
127
. Similarly, the complement signal /PWM OUT
120
will pass through a second delay
124
as /PWM DLY before reaching one of two inputs to the second AND gate
128
while the same /PWM OUT
120
signal is passed through to the other input of the second AND gate
128
. The resulting output of AND gate
128
is signal PWM BOTTOM
129
. PWM TOP
127
and PWM BOTTOM
129
are the two input signals to inverter
190
. PWM TOP
127
and PWM BOTTOM
129
will drive separate gate drives
132
,
133
inside the inverter
190
which with additional hardware (not shown and not germane to the present invention) will result in the generation of a desired AC waveform.
Typical DC to AC inverters (such as inverter
190
) require a “dead” period (deadtime
130
) between turning off one switch (such as a transistor switch) and turning on the other switch to ensure that the two switches (i.e., top switch
134
and bottom switch
136
shown in
FIG. 1
) do not conduct simultaneously which could damage the load. The required deadtime
130
is achieved by adding delay periods to the rising edges of the PWM OUT
119
and /PWM OUT
120
signals via passing these signals through the first and second delays
122
,
124
.
By adding the necessary delays to avoid having multiple switches conduct simultaneously and risking damages to the load, other problems are created.
FIG. 2
shows the relative phase of the signals PWM OUT
119
and PWM TOP
127
in a normal condition, i.e., when the deadline
130
is shorter in duration than the duration of the PWM OUT
119
. Here, in this normal condition, the two signals PWM OUT
119
and PWM TOP
127
are synchronized with each other. But, as shown in
FIG. 3
, when the deadtime
130
is longer in duration than PWM OUT
119
, the PWM OUT
119
signal is out of synchronization with PWM TOP
127
signal. This condition can cause damages to the load (such as the inverter
190
) because the PWM OUT
119
and PWM TOP
127
signals which control the gate drive to switch
134
are out of synchronization with each other. A similar out of synchronization condition can result between /PWM OUT
120
and PWM BOTTOM
129
with damaging effects to the load if the deadtime duration is longer the /PWM OUT
120
. As such, it would be desirable to provide a solution in the form of a PWM protection circuit (within the PWM controller) for masking the out of synchronization condition.
A second problem with the prior art controller circuit results when the absolute value of the PWMDATA
101
amplitude is outside the maximum or minimum amplitude range (±MaxCount) of the high frequency triangular carrier signal CARRIER CNT
102
as seen from time period t5 through t8 in FIG.
4
. When the PWMDATA
101
is out of the ±MaxCount range of the CARRIER CNT
102
signal, the comparator
114
makes an incorrect comparison and generates an inappropriate PWM OUT
119
(and hence is also unable to achieve a complement signal, /PWM OUT
120
, appropriately). This results in a loss of the PWM duty cycle, resulting in a perturbation to the frequency spectrum of the desired AC waveform. A prior art solution to this second problem is to use a software comparison algorithm to compare the PWM DATA
101
with the ±MaxCount range of the CARRIER CNT
102
signal. However, this software adds complexity and may require too much CPU or DSP processing time. Accordingly, it would be desirable to provide a solution which would not require complicated software or additional CPU/DSP processing time.
SUMMARY OF THE INVENTION
The present invention is directed to protection circuitry for pulse width modulation control of inverters. The present invention overcomes the problem of PWM duty cycle loss of the prior art by incorporating a Carrier Range Regulation Circuit to force the values of the PWMDATA to be within the maximum and minimum amplitude range (i.e., within ±MaxCount) of the CARRIER CNT without software compensation. The Carrier Range Regulation Circuit comprises an Absolute Value Converter, a Comparator, a Selector and a Sign Assigner Circuit. The Absolute Value Converter takes the absolute value of the PWMDATA and inputs this value to the Comparator and the Selector. Subsequently, as shown in
FIG. 6
, the Sign Assigner Circuit will reverse this process by reinstalling the appropriate sign value. The circuitry of such a sign assigner circuit is known to one of ordinary skill in the art.
The Comparator compares this input with its other input, the MaxCount of the CARRIER CNT signal. If the PWMDATA absolute value is less than or equal to the MaxCount value, the resulting output of the Comparator is 0. If the PWMDATA absolute value is greater than the MaxCount value, the resulting output of the Comparator is 1. The output of the Comparator is then routed to the Selector as another input. A “0” input into the Selector signifies that the PWMDATA value is selected as the output (PWMCMD PRE) of the Carrier Range Regulation Circuit. A “1” input into the Selector signifies that the MaxCount value is selected as the output (PWMCMD PRE) of the Carrier Range Regulation Circuit. Hence, this selection manner ensures against out of bound PWM waveforms and thus prevents the loss of PWM duty cycle and perturbation to the frequency spectrum of the desired AC waveform.
Additionally, the present invention may include a PWM Pulse Feedback Circuit and a Deadtime Circuit which work in combination to overcome the prior art's out of synchronization problem resulting from a deadtime duration that is not shorter than the duration of the PWM PULSE signal. The Feedback Circuit includes a Differential Circuit
2
and a Sensor Circuit working in combination to monitor the PWM pulse signals that are generated. In one embodiment, the Differential Circuit
2
includes a plurality of clocked D-flip flop dev
McDermott Will & Emery LLP
Nguyen Matthew V.
Sodick Co. Ltd.
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