1979-01-19
1981-06-23
Heyman, John S.
328 61, 328112, 328129, H03K 708
Patent
active
042753546
ABSTRACT:
First and second counters in a pulse width modulating circuit, whose respective outputs determine the trailing and leading edges of a pulse width modulated signal, count input clock pulses at a constant speed. The number of the pulses applied to the second counter during a cycle relative to the number of the pulses applied to the first counter is increased or decreased by one in response to a modulating pulse to change the counting phase of the second counter thereby changing the width of the pulse width modulated signal. Gates freeze the phases of the two counters at minimum and maximum pulse widths of the pulse width modulated signal to avoid abrupt jumps from minimum to maximum or vice versa.
REFERENCES:
patent: 3697879 (1972-10-01), Holliday
patent: 3958182 (1976-05-01), Sauthier
patent: 4109210 (1978-08-01), Gerlach et al.
patent: 4166246 (1979-08-01), Matt
Mogi Takao
Suematsu Masayuki
Taki Akira
Eslinger Lewis H.
Heyman John S.
Sinderbrand Alvin
Sony Corporation
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