Pulse width modulated self-clocking and self-synchronizing data

Details Pulse width modulated self-clocking and self-synchronizing data Pulse width modulated self-clocking and self-synchronizing data

1989-09-29

1992-08-18

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375 22, 370 9, 332109, 34087024, H03K 708, H03K 908

Patent

active

051406110

ABSTRACT:
Transmissions of synchronous digital data from a master control unit (50A) to a slave, network termination unit (50B) are via a pulse width modulated data stream including pulse width modulated binary code pulses (20, 22) with a pulse width modulated synchronization pulse (24) all of which have a preselected leading edge transition (28) at the same point in each cycle of a master clock signal. A clock signal is derived at the network termination unit (50B) from the received pulse width modulated binary data stream for decoding and for nonself-clocking, synchronous transmissions from the slave, network termination unit (50B) to the master, control unit (50A). The phase synchronization pulse (24) is employed to maintain phase sychronization between the transmission to and from the control unit (50A).

REFERENCES:
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patent: 4651114 (1987-03-01), Steinmayer et al.
patent: 4885738 (1989-12-01), Bowers et al.

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