Pulse width detection

Details Pulse width detection Pulse width detection

2000-10-13

2002-06-04

Miska, Vit (Department: 2859)

Horology: time measuring systems or devices

Time interval

Electrical or electromechanical

C368S120000, C377S020000

Reexamination Certificate

active

06400650

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to pulse width detectors and more particularly to apparatus and methods for measuring pulse widths in semiconductor circuits during the manufacture thereof.
As is known in the art, in the manufacture of semiconductor circuits, a significant cost is incurred in testing such circuits. Testing is necessary to detect manufacturing or design defects effecting operational characteristics of the circuits. For example, many semiconductor circuits, such as Dynamic Random Access Memories (DRAMs), use internally-generated pulses to convey information. Different pulse widths (i.e., time durations) convey different information. Because the pulses can control various functions of the circuit, it is desirable to test the circuit to ensure that all of the pulses produced by the circuit have proper pulse widths.
Much of the cost for testing these circuits is the result of the cost of the test equipment. With pulse widths typically on the order of 2-4 ns, the test equipment needs to have a very fine time resolution in order to determine whether the pulse has an acceptable pulse width. If the pulse width is measured by probing a conductor carrying the pulse and the test equipment used to sample the pulse on the conductor, then the test equipment needs to sample the pulse at a frequency on the order of 1 GHz (i.e., a sampling period of {fraction (1/10)}
9
seconds or 1 nanosecond (ns)) in order to provide a time duration resolution on the order of 1 ns. Test equipment having operational or sampling frequencies this high is typically very expensive.
SUMMARY OF THE INVENTION
In accordance with one feature of the invention, a semiconductor circuit is provided including operational circuitry configured to produce a signal to be tested. Test circuitry is provided to sense the signal. The test circuitry provides indications of whether a pulse in the sensed signal has a time duration at least as long as corresponding, different, time durations. The indications effectively divide the pulse into a plurality of time cells or windows indicative of different ranges of time durations, with differences between a maximum time duration and a minimum time duration of each window being a timespan of that window. The indications indicate which of the windows includes the time duration of the pulse. The indications provided by the test circuitry are at a frequency, f
1
, that is lower than a frequency, f
2
, that is defined by an inverse of a shortest one of the timespans. The test circuitry is operated independently of a clock signal having a clock frequency f
CLK
that is greater than the frequency f
2
.
With such an arrangement, a signal, which may include high-frequency components, in the semiconductor circuit can be tested at a relatively high effective sampling frequency, f
s
, and a characteristic (e.g., a level or a pulse width) of the signal can be expressed in a format having a lower frequency, f
c
, thereby enabling an effectively high-frequency sampling without requiring expensive high-frequency test circuitry.
In accordance with another feature of the invention, a semiconductor circuit is provided including operational circuitry configured to produce a signal, having at least one pulse, to be tested. Test circuitry is provided to sense the signal at a high effective sampling frequency and to produce an indication of a characteristic of the pulse or pulses. The indication of the characteristic is at a frequency that is lower than the effective sampling frequency. The test circuitry does not need, and is therefore independent of a clock signal having a clock frequency that is greater than the effective sampling frequency.
With such an arrangement, high-frequency performance of circuit components and high-frequency quality of signals in the circuit can be measured with lower-frequency test equipment.
In accordance with another feature of the invention, a semiconductor circuit is provided including circuitry for producing a pulse. A plurality of, n, delay elements is provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output thereof, with the pulse being received at respective outputs thereof at correspondingly different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding one of the delay elements. Each detector is adapted to set an output state to a predetermined one of a plurality of states in response to detection of a portion of the pulse.
With such an arrangement, a pulse width can be determined to be within a range of time durations having a timespan 1/f
s
, and expressed in a format that is detectable at a frequency f
c
that is lower than the frequency f
s
.
In accordance with another feature of the invention, the outputs of the detectors are coupled to output pins of the semiconductor circuit.
With such a structure, pulse widths can be detected by a relatively inexpensive tester after the semiconductor circuit has been packaged.
In accordance with another feature of the invention, a semiconductor circuit is provided including operational circuitry, delay elements, and a decoder. The operational circuitry produces a pulse having a pulse width. The pulse enables and disables the delay elements in parallel, which provide the pulse to a plurality of output ports at different times. The decoder receives the pulse from the delay element output ports and provides a signal to indicate a time duration window that includes the pulse width.
With such a structure, relatively low-frequency signals can be used to indicate that a window, or which window, of time durations includes the pulse width. For example, such signals can include an analog DC voltage on a single line, and/or serial digital binary DC voltage levels on a single line, and/or digital binary DC voltage levels on multiple lines, e.g., in parallel.
In accordance with another feature of the invention, a semiconductor circuit is provided comprising circuitry for producing a pulse, n serially coupled delay elements, and n latches. The delay elements are enabled and disabled in parallel by leading and trailing edges, respectively, of the pulse, and serially transmit the pulse from delay element inputs to delay element outputs thereof with associated time delays. Each latch is adapted to set its output to a first predetermined state if the latch receives a portion of the pulse at its input, which is coupled to a corresponding delay element input. At least one of the latches is adapted to set its output to a second predetermined state if the latch receives a portion of the pulse from the output of a last one of the n delay elements.
With such an arrangement, indications are provided as to whether any pulse is produced and, if a pulse is produced, which of n bounded windows of time durations a width of the pulse is within, or that the width is longer than a maximum delay of the delay elements.
In accordance with another feature of the invention, a semiconductor circuit is provided comprising circuitry for providing a pulse, n delay elements, and n−1 latches. The delay elements are adapted to be activated and deactivated by a first edge and a second edge, respectively, of the pulse received in parallel at corresponding enable ports thereof. Each delay element is adapted to transmit the pulse, with a corresponding time delay, from a delay element input port to a delay element output port thereof. Each latch has a latch input port, coupled to a corresponding delay element input port, and a latch output port, and is adapted to provide a DC signal to the latch output port if the first edge of the pulse is received at the latch input port.
In accordance with another feature of the invention, a semiconductor circuit is provided including operational circuitry, a delay element, and a latching element. The operational circuitry provides a pulse. The delay element is selectively coupled to the operational circuitry, is enabled and disabled by the pulse, and transmits

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