Pulse width control circuit

Details Pulse width control circuit Pulse width control circuit

1999-03-22

2002-12-10

Korzuch, William (Department: 2753)

Dynamic information storage or retrieval

Binary pulse train information signal

Binary signal processing for controlling recording light...

C369S053340, C369S124140, C369S059200, C369S060010

Reexamination Certificate

active

06493305

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to a pulse control circuit, and, more particularly, to a pulse width control circuit including a delay circuit having a plurality of delay elements. The pulse width control circuit is suitable for use in a disk recording control circuit where the recording timing of recording marks is adjustable.
Optical disk devices and magneto-optical disk devices that can reproduce and write data are known. Data is written on a recording medium by recording a recording mark corresponding to a data modulation signal using a laser device.
For example, in a CD-R (compact disc-recordable), an EFM (Eight to Fourteen Modulation) encoder converts write data into an EFM signal, and the laser device records a recording mark corresponding to the EFM signal on the disk. However, the recording status varies in accordance with the type of recording medium and the rotational speed of the disk. In this case, a desired recording mark cannot be recorded simply by supplying the EFM signal to the laser device. As an experiment for recording the desired recording mark, delaying the rising (leading) edge and falling (trailing) edge of the EFM signal has been performed. For example, to delay the EFM signal, a delay circuit including a plurality of logic circuits such as D flip-flops that operate in synchronism with a clock signal is used.
The EFM signal is synchronized with a reference signal called an EFM clock signal and has a pulse width of three to eleven cycles of the EFM clock signal. Accordingly, the clock signal applied to the D flip-flop of the delay circuit should be faster than the EFM clock signal. For example, when the delay circuit has sixteen stage resolution, a clock signal having sixteen times the speed of the EFM clock signal is required.
Thus, the required frequency of the EFM clock signal is relatively high. For example, the frequency of the EFM clock signal is “17.28 MHZ” for 4× speed and “34.56 MHZ” for 8× speed. Accordingly, a clock signal of “276.48 MHZ” should be applied to the D flip-flop for 4× speed and a clock signal of “552.96 MHZ” should be applied to it for 8× speed. Today, it is impossible to supply such a high-speed clock signal, and it is also exceedingly difficult to obtain a logic circuit that stably operates in synchronism with the high-speed clock signal.
Further, the delay circuit is sensitive to external effects, such as power fluctuations and temperature changes. Accordingly, when a very short pulse width is desired, it is difficult to control the delay circuit with high accuracy.
It is an object of the present invention to provide a pulse width control circuit which generates a pulse signal without using a high-speed clock signal.
SUMMARY OF THE INVENTION
In a first aspect, the present invention provides a pulse width control circuit including a first delay circuit which includes a plurality of first delay elements for delaying a pulse signal and generating a plurality of first delay pulse signals. A first selector selects one of the plurality of first delay pulse signals. A first logic circuit receives the selected first delay pulse signal and the pulse signal and generates a first logic output signal. A second delay circuit includes a plurality of second delay elements for delaying the first logic output signal and generating a plurality of delay logic signals. A second selector selects one of the plurality of delay logic signals. A second logic circuit receives the selected delay logic signal and the first logic output signal and generates a second logic output signal. The first and second logic circuits include a logic AND circuit and a logic OR circuit.
In a second aspect, the present invention provides a disk recording control circuit including a pulse width control circuit for receiving a pulse modulation signal and generating a pulse width controlled modulation signal in accordance with first and second selection signals related to a media type and/or a rotational speed of a recording medium. The pulse width control circuit includes a first delay circuit which includes a plurality of first delay elements for delaying the pulse modulation signal and generating a plurality of delayed pulse modulation signals. A first selector selects one of the plurality of delayed pulse modulation signals in accordance with the first selection signal. A first logic circuit receives the selected delayed pulse modulation signal and the pulse modulation signal and generates a logic output signal. A second delay circuit includes a plurality of second delay elements for delaying the logic output signal and generating a plurality of delayed logic signals. A second selector selects one of the plurality of delayed logic signals in accordance with the second selection signal. A second logic circuit receives the selected delayed logic signal and the logic output signal and generates the pulse width controlled modulation signal. The first and second logic circuits include a logic AND circuit and a logic OR circuit.
In a third aspect, the present invention provides a pulse width control circuit including a synchronous circuit for receiving a pulse signal and generating a delayed pulse signal which is synchronized with a reference clock signal and is delayed by a predetermined period. A first logic circuit receives the delayed pulse signal and the pulse signal and generates a first logic operation pulse signal. A selection circuit receives the delayed pulse signal and the first logic operation pulse signal and selects one of the delayed pulse signal and the first logic operation pulse signal in accordance with information indicating a decrease or increase of the pulse width. A first delay circuit includes a plurality of first delay elements for delaying the selected pulse signal and generating a plurality of first delayed pulse signals. A first selector selects one of the plurality of first delayed pulse signals. A second logic circuit receives the selected first delayed pulse signal and the selected one of delayed pulse signal and the first logic operation pulse signal from the selection circuit and generates a second logic operation pulse signal. A second delay circuit includes a plurality of second delay elements for delaying the second logic operation pulse signal and generating a plurality of delayed logic signals. A second selector selects one of the plurality of delayed logic signals and generates a pulse width controlled pulse signal.
In a fourth aspect, the present invention provides a pulse width control circuit including a synchronous circuit for receiving a pulse signal and generating a delayed pulse signal which is synchronized with a reference clock signal and is delayed by a predetermined period. A first logic circuit receives the delayed pulse signal and the pulse signal and generates a logic operation pulse signal. A selection circuit receives the delayed pulse signal and the logic operation pulse signal and selects one of the delayed pulse signal and the logic operation pulse signal in accordance with information indicating a decrease or increase of the pulse width. A first delay circuit includes a plurality of first delay elements for delaying the selected pulse signal and generating a plurality of first delayed pulse signals. A first selector selects one of the plurality of first delayed pulse signals. A second delay circuit includes a plurality of second delay elements for delaying the selected first delayed pulse signal and generating a plurality of second delayed pulse signals. A second selector selects one of the plurality of second delayed pulse signals. A second logic circuit receives the selected second delayed pulse signal and the selected one of the delayed pulse signal and the logic operation pulse signal from the selection circuit and generates a pulse width controlled pulse signal.
In a fifth aspect, the present invention provides a disk recording control circuit including a pulse width control circuit for receiving a pulse modulation signal and generating a pulse width

Affiliated with

Also associated with

Rating

Pulse width control circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pulse width control circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pulse width control circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2981244