Pulse-to-static conversion latch with a self-timed control circu

Details Pulse-to-static conversion latch with a self-timed control circu Pulse-to-static conversion latch with a self-timed control circu

1997-01-06

1999-10-26

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327202, 327203, H03K 3289

Patent

active

059735295

ABSTRACT:
A low-power pulse-to-static conversion latch circuit is disclosed. The circuit includes self-timed control and an n-bit latch array both designed utilizing self-resetting CMOS circuit techniques. The self-timed feature of the control requires only one system clock input. The evaluation, reset and write-enable controls are all generated within a control macro. The latch is level sensitive scan design (LSSD) compatible and complies with self-resetting CMOS (SCRMOS) test modes. Use of these latches facilitates the synchronization, pipelined operation, power-management, and testing of advanced digital systems employing a mix of static and dynamic circuits to achieve high performance.

REFERENCES:
patent: 5012246 (1991-04-01), Chung et al.
patent: 5459421 (1995-10-01), Shaw
patent: 5619157 (1997-04-01), Kumata et al.
patent: 5712826 (1998-01-01), Wong et al.

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