Pulse or digital communications – Systems using alternating or pulsating current
Reexamination Certificate
1999-09-08
2003-01-07
Le, Amanda T. (Department: 2634)
Pulse or digital communications
Systems using alternating or pulsating current
C375S295000, C327S291000, C307S106000
Reexamination Certificate
active
06504876
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pulse signal generating apparatus and a pulse signal generating method, and more specifically, to a technique capable of producing a desired pulse signal under a program control.
2. Description of the Related Art
Conventionally, in a microcomputer application apparatus such as a video player, an audio player, various type of pulse signal generating apparatuses are used to control the operation of the apparatus. Such a pulse signal generating apparatus is well known in which a pulse signal having an, optional waveform can be generated under a program control.
FIG.1
shows a blockidiagram of one example of such a conventional pulse signal generating apparatus. This pulse signal generating apparatus is composed of a timer
50
, a comparator
51
with a register (will be simply referred to as a “comparator
51
” hereinafter), a buffer
52
, a latch
53
, a port
54
and a central processing unit (will be simply referred to as a “CPU” hereinafter)
55
. The timer
50
is composed of a counter that the content is incremented at every predetermined time interval. A timer count value outputted from this timer
50
is supplied to a comparator
51
.
The comparator
51
is composed of a register and a comparator (illustrating neither). A timing data from the CPU
55
is set in the register. This timing data is used to determine a transition timing of a pulse signal to be generated. The comparator compares the timing data in the register and the timer count value outputted from the timer
50
, and outputs a coincidence signal when the timing data in the register coincides with the timer count value outputted from the timer
50
. The coincidence signal outputted from this comparator
51
is supplied to the buffer
52
, and is also supplied to the CPU
55
as an interruption signal.
The buffer
52
stores a level data sent from the CPU
55
. The level data is used to determine the level of the pulse signal to be generated in this pulse signal generating apparatus. The level data stored in this buffer
52
is transferred to the latch
53
when the coincidence signal is supplied from the comparator
51
. The latch
53
holds the level data until a new level data is supplied from the buffer
52
. The content of this latch
53
is send to a external device (not shown) through the port
54
.
Subsequently, an operation of the conventional pulse signal generating apparatus with employment of the above-explained arrangement will now be described with reference to the explanatory diagram shown in FIG.
2
.
First, the CPU
55
sets a timing data TD
1
into the register included in the comparator
51
and sets “1” as level data into the buffer
52
. In this condition, the timer
50
begins a counting operation. Then, when the data outputted from the timer
50
coincidences with the timing data TD
1
stored in the comparator
51
, the comparator
51
outputs an coincidence signal.
As a result, the level data of “1” stored in the buffer
52
is transferred to the latch
53
. Through above operations, the level of the pulse signal outputted from the port
54
becomes a high level (hereinafter, is called “H level”) at timing T
1
. Also, the coincidence signal outputted from the comparator
51
is supplied to the CPU
55
as the interruption signal. In response to this interruption signal, the CPU
55
sets a timing data TD
2
in the comparator
51
and also sets level data of “0” in the buffer
52
. In this condition, the counting operation of the timer
50
is continuously executed, and when the data outputted from the timer
50
coincidences with the timing data TD
2
stored in the comparator
51
, the comparator
51
outputs an coincidence signal.
As a result, the level data of “0” in the buffer
52
is transferred to the latch
53
. Through above operations, the level of the pulse signal outputted from the port
54
becomes a low level (hereinafter, is called “L level”) at timing T
2
. Also, the coincidence signal outputted from the comparator
51
is supplied to the CPU
55
as an interruption signal. In response to this interruption signal, the CPU
55
sets a timing data TD
3
in the comparator
51
and also sets level data of “1” in the buffer
52
. Subsequently, while operations similar to the above operations are repeatedly carried out, such a pulse signal as shown in
FIG. 2
is generated.
According to this conventional pulse signal generating apparatus, because the timing data to be set in the comparator
51
and the level data to be set in the buffer
52
are suitably changed into, the pulse signal having a desired waveform (pulse width) can be generated.
As a related conventional technology, Japanese Laid Open Patent Disclosure (JP-A-Heisei 2-199503) discloses “A MICROCOMPUTER”. This microcomputer equips a memory which stores at least one of the program and the data, a central processing unit which executes calculation processing in accordance, with the program stored in the memory, and a pulse producing circuit which generates a pulse signal based on the data set from this central processing unit and outputs the pulse signal. The pulse producing circuit of this microcomputer equips with a counter, a comparator with a plurality of registers, a first pulse output circuit, an arbitration circuit, a second pulse output circuit and a selection circuit.
The content of the counter is renewed based on the externally supplied clock. The comparator with the plurality of registers compares the data set from the central processing unit and the content of the counter, and when the data set from the central processing unit coincidences with the content of the counter, outputs a coincidence signal. The first pulse output circuit is set/reset in response to the coincidence signal outputted from the comparator with the plurality of registers and externally outputs a first output pulse. The arbitration circuit arbitrates the coincidence signals outputted from a part of the comparator with the plurality of registers based on the fixed priority, and then outputs a reading signal for reading data to the other part of the comparator with the plurality of registers. The second pulse output circuit outputs the data read from the comparator with the registers by using the reading signal supplied from the arbitration circuit to outside as the second signal pulse. The selection circuit makes either of the first and the second pulse output circuit operate.
According to this microcomputer, when the data that defines the rising time and the falling time of each phase is stored in the comparator with the plurality of registers, the comparator with the plurality of registers compares the stored data and the content of the counter. Then, the first pulse output circuit is set/reset by the coincidence signal outputted from the comparator with the plurality of register. As a result, such a PWM pulses signal that the conventional microcomputer generates is obtained. Also, if the output timing data which shows the output time of the data is stored into a part of the comparator with the plurality of registers and data to be outputted is stored in another part of the comparator with the plurality of registers, so-called real-time processing to output desired data in the desired timing can be performed. In this case, when the same output timing data is stored in the comparator with the plurality of registers, the arbitration circuit arbitrates these timing based on predetermined priority. As a result, the conflict among the data can be prevented.
Also, Japanese Laid Open Patent Disclosure (JP-A-Heisei 8-76875) discloses “MICROCOMPUTER APPLICATION SYSTEM”. In this microcomputer application system, a counter is cleared when the write pulse detecting station detects a write cycle signal of the CPU. Then, the content of the counter is compared with the content of the control register at a comparator, and an idle state signal is outputted from the state detection signal output section in case of the coincidence. As a result, when the CPU is in the
Le Amanda T.
NEC Corporation
Whitham Curtis & Christofferson, PC
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