Pulse or digital communications – Cable systems and components
Reexamination Certificate
1998-07-07
2001-01-30
Vo, Don N. (Department: 2734)
Pulse or digital communications
Cable systems and components
C375S286000, C327S126000
Reexamination Certificate
active
06181748
ABSTRACT:
TECHNICAL FIELD
The present invention relates to tele-communication interface circuit apparatus and methods. More particularly, the present invention relates to tele-communication interface circuit apparatus and methods for shaping pulse signals. Even more particularly, the present invention relates to tele-communication interface circuit apparatus and methods for shaping pulse signals for use in ISDN U-interface (integrated service digital network user interface) applications.
BACKGROUND OF THE INVENTION
Conventional pulse shaper presented in ‘IEEE Transactions on Communication Technology’, Vol. COM-16, No. 1, February, 1968, pp 81-93, is comprised of a resistor arrangement, digital input controlled shift register, and a summing node. The disadvantages of such pulse shaper are that only one polarity output signal can be generated and requires too many resistors.
The pulse shaper presented in U.S. Pat. No. 4,814,637, named ‘pulse shaper,’ is a well known pulse shaper for ISDN U-interface. The pulse shaper disclosed in U.S. Pat. No. 4,814,637 includes a control signal generator, a summing network including a number of charging capacitors, a controll able switch arrangement, a plurality of logic circuits coupled between the control signal generator and respective ones of the controllable switch arrangement. The respective charging capacitor associated with a respective switch exchanges a component charge with the summing capacitor that corresponds to the step to be formed on the occurance of the particular control signal. The main disadvantage of such pulse shaper is that it requires a series of complex switch topology and as many number of charging capacitor as the steps of the one output staircase-type slope.
BRIEF SUMMARY OF THE INVENTION
The pulse shaper of the present invention includes a couple of control clock generators, a clock-controlled fully differential switched-capacitor integrator, a fully differential sample and hold circuit, and a fully differential line driver/Rauch lowpass filter. The control clock generator generates a specific number of pulses which are responsive to four-level digital 2B1Q coded signals (quarternary signals), to control the switched-capacitor integrator and a cyclic clock to control the sample and hold circuit. The final Rauch lowpass filter is utilized to attenuate, the out-of-band signal power (above 500 kHz) to fit the ANSI specifications.
The main advantage of the present invention is that it requires only a couple of charging capacitors in fully differential structure to perform the identical leading and trailing slopes staircase-type analog waveform. Thus, the total circuit complexity and solid-state area can be greatly reduced. Further, in cooperation with the sample and hold circuit, the spikes generated during the switch's on/off transitions can be easily eliminated such that the formed output signal's linearity will be improved.
REFERENCES:
patent: 4754386 (1988-06-01), Weerd
patent: 4814637 (1989-03-01), Roessler et al.
patent: 5200751 (1993-04-01), Smith
patent: 5598438 (1997-01-01), Lepping
Herbert B. Voelcker. “Generation of Digital Signaling Waveforms.” IEEE Transactions on Communication Technology, vol. Com-16, No. 1, Feb. 1968. pp. 81-93.
Chen Jhy-Rong
Lin Hsan-Fong
Yang Wen-Fu
LaRiviere Grubman & Payne, LLP
Macronix International Co.
Vo Don N.
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