Pulse rejection circuit model program and technique in VHDL

Details Pulse rejection circuit model program and technique in VHDL Pulse rejection circuit model program and technique in VHDL

1998-03-25

2000-10-31

Teska, Kevin J.

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

703 13, G06F 1750

Patent

active

061416312

ABSTRACT:
A method determines the behavior of a logic cell that receives input signals resulting in a narrow pulse or "glitch." If the pulse width of the output pulse is narrower than a pulse rejection period, the output pulse is rejected and is not propagated to subsequent logic cells connected to the output. The method employs a first internal logic cell model which is assigned an inertial delay function, and a second internal logic cell model which is assigned a transport delay function. In combination, the first and second logic cell models result in an effective propagation delay value, subject to the pulse rejection feature. An exemplary VHDL model is disclosed. A program product embodies a logic cell model in VHDL providing pulse rejection capabilities for output pulses with pulse width smaller than a pulse rejection period.

REFERENCES:
patent: 4656580 (1987-04-01), Hitchcock et al.
patent: 4787062 (1988-11-01), Nei et al.
patent: 5091872 (1992-02-01), Agrawal
patent: 5418735 (1995-05-01), Saitoh
patent: 5657239 (1997-08-01), Grodstein et al.
patent: 5875111 (1999-02-01), Patel

Affiliated with

Also associated with

Rating

Pulse rejection circuit model program and technique in VHDL does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pulse rejection circuit model program and technique in VHDL, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pulse rejection circuit model program and technique in VHDL will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2064527