Pulse rate multiplying circuitry

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307225R, 235 92DM, H03B 1900, H03K 500

Patent

active

043319246

ABSTRACT:
Pulse rate multiplying circuitry is responsive to an input pulse train for generating an output pulse train having a number of pulses which is a selected multiple of the number of pulses in the input pulse train. That is, the pulse rate multiplying circuitry produces exactly a selected multiple of output pulses for each input pulse so that the frequency of the output pulse train is the selected multiple of the frequency of the input pulse train. Preferably, the pulses in the output pulse train are uniformly distributed in time. That is, the output pulses generated in response to each input pulse are equally spaced and evenly distributed over the time interval between consecutive input pulses. The pulse rate multiplying circuitry includes an up/down counter incremented by pulses in the input pulse train. The up/down counter is decremented by feedback pulses generated by a feedback circuit including a digital/analog converter, a voltage controlled oscillator controlled by a counter empty detect circuit, and a divide-by-N circuit arranged in a frequency locked loop with the up/down counter. The voltage controlled oscillator generates an output pulse train having a frequency which is a selected multiple of the frequency of the input pulse train, the selected multiple being determined by the count preset into the divide-by-N circuit. The counter empty detect circuit enables the voltage controlled oscillator when a count is present in the up/down counter and disables the voltage controlled oscillator when the count in the up/down counter is zero, thereby assuring that the output pulse train has exactly the selected multiple of the number of pulses in the input pulse train. Preferably, a digitally selected filter is included in the feedback circuit between the digital/analog converter and the voltage controlled oscillator, thereby assuring that the pulses in the output pulse train are uniformly distributed in time. Other features are also disclosed.

REFERENCES:
patent: 3411102 (1968-11-01), Sommerud et al.
patent: 3617902 (1971-11-01), Bauer
patent: 3673391 (1972-06-01), Lougheed
patent: 3935538 (1976-01-01), Kizler et al.
patent: 4053839 (1977-10-01), Knoedl
patent: 4086471 (1978-04-01), Takahashi

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