Pulse processing circuit and frequency multiplier circuit

Details Pulse processing circuit and frequency multiplier circuit Pulse processing circuit and frequency multiplier circuit

2005-05-31

2005-05-31

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S278000, C327S288000

Reexamination Certificate

active

06900684

ABSTRACT:
PMOS transistors P1-Pn and PMOS transistors P1′-Pn′ are respectively connected in series between a supply voltage terminal VD and output terminals OUTB, while NMOS transistors N1-Nn and NMOS transistors N1′-Nn′ are respectively connected in series between the output terminals OUTB and a ground terminal G. Input terminals S1-Sn are respectively connected to the gates of the PMOS transistors P1′-Pn′ and NMOS transistors N1-Nn, and they are respectively connected to the gates of the PMOS transistors P1-Pn and NMOS transistors N1′-Nn′ through corresponding inverters IV1-IVn.

REFERENCES:
patent: 5955902 (1999-09-01), Takada et al.
patent: 5959486 (1999-09-01), Choi
patent: 6005420 (1999-12-01), Yoshizawa et al.
patent: 6121817 (2000-09-01), Yang et al.
patent: 6122492 (2000-09-01), Sears
patent: 6340910 (2002-01-01), Saeki
patent: 6381192 (2002-04-01), Ahn et al.
patent: 6525569 (2003-02-01), Leon
patent: 6525584 (2003-02-01), Seo et al.
patent: 1279550 (2001-01-01), None
patent: 2001-209454 (2001-08-01), None
Communication from Chinese Patent Office re: counterpart application with English Translation.

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