Pulse output direct digital synthesis circuit

Details Pulse output direct digital synthesis circuit Pulse output direct digital synthesis circuit

2007-05-28

2010-11-30

Ngo, Chuong D (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C327S105000

Reexamination Certificate

active

07844650

ABSTRACT:
A clock signal generator responsive to a frequency control word and a reference clock signal having a reference clock frequency fref. The clock signal generator generates an output clock signal having a frequency fgen, wherein fgenis less than fref. A modulo-N counter accepts the reference clock signal as input. The modulo-N counter generates a phase-indication signal of the reference clock. The phase indication signal has N clock phases repeating at a frequency of fref/N. An accumulator iteratively accumulates a frequency control word into a modulo-N adder and produces an accumulated value. One or more bits of the accumulated value is fed-back into the modulo-N adder for adding modulo N to the accumulated value in the next iteration. N of the modulo-N adder is the same integer as in the modulo-N counter. A clock edge selector receives as inputs the phase indication signal and one or more bits of the accumulated value and by comparing the inputs selects an edge of the reference clock signal upon which to toggle the state of the output clock signal. The clock edge selector preferably selects the edge from: (i) only rising edges of the reference clock signal, (ii) only falling edges of the reference clock signal or (iii) both rising and falling edges of the reference clock signal. The clock edge selector selects between a rising edge and a falling edge of the reference clock signal preferably based on one or more bits of the accumulated value.

REFERENCES:
patent: 4672329 (1987-06-01), Hikawa
patent: 5160894 (1992-11-01), Westwick
patent: 5394106 (1995-02-01), Black et al.
patent: 5528308 (1996-06-01), Alelyunas et al.
patent: 5673212 (1997-09-01), Hansen
patent: 5812832 (1998-09-01), Horne et al.
patent: 5931891 (1999-08-01), Landry
patent: 5974891 (1999-11-01), Uchikawa et al.
patent: 6064241 (2000-05-01), Bainton et al.
patent: 6107843 (2000-08-01), de Gouy et al.
patent: 6642754 (2003-11-01), Dobramysl et al.
patent: 7242225 (2007-07-01), Klage
patent: 2003/0058004 (2003-03-01), Stengel et al.
patent: WO03/027847 (2003-04-01), None
Michael S. McCorquodale, Mei Kim Ding, Richard B. Brown, “Top-Down and Bottom-Up Approaches to Stable Clock Synthesis” International Conference on Electronic Circuits and Systems, Sharjah, United Arab Emirates pp. 575-579 2003.
Goldberg, Bar-Giora, Digital Frequency Synthesis Demystified: DDS and fractional-N PLLs, LLY Technology Publishing, 1999.

Affiliated with

Also associated with

Rating

Pulse output direct digital synthesis circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pulse output direct digital synthesis circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pulse output direct digital synthesis circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4224149