Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-10-14
2001-12-04
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S199000, C327S175000, C327S292000, C327S212000, C375S354000
Reexamination Certificate
active
06326829
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to integrated circuit clock circuitry and more particularly to clock circuitry including at least one and usually many latches driven in parallel by a one shot that derives a pulse train in response to clock waves having about a 50% duty cycle, wherein each pulse in the pulse train (1) is initiated in response to a clock wave transition, and (2) persists after the transition has been completed for less than a half cycle of each clock cycle.
BACKGROUND ART
Most integrated circuits include one of two different types of clock arrangements. These clock arrangements are responsive to clock waves generally derived from sources external to the integrated circuit chip. The clock waves typically have about a 50% duty cycle, such that during half of each cycle of the clock wave, the clock wave has a high value and during the other 50% of each cycle, the clock wave has a low amplitude.
In one type of prior art integrated circuit clock circuitry, the circuits respond to an edge of the clock wave during each cycle. Latches and other circuit elements are activated in response to a leading or trailing edge of a clock.
A problem with the edge responsive integrated circuit, when it is used in relatively large integrated circuit chips (e.g., chips having sides 2 centimeters long) and operating at relatively high frequencies (e.g., 1 GHz), is that the clock edges arrive at the various circuits on the chips at different times. This phenomenon, generally known as clock skew, results in poor synchronization of circuits on different portions of the integrated circuit chip. The poor synchronization can result in an improper transfer of data signals between the circuits on the chip. The problem is compounded because the propagation delay of the clock wave to different portions of the chip is variable, as a function of (1) processing variations of different circuit elements on different portions of the chip, (2) temperature and (3) power supply voltage. The temperature and power supply voltages vary as a function of time and spatial location of circuits on the chip.
“Flow-through-Latch and Edge-Triggered Flip-Flop Hybrid Elements,” Partovi, et al., ISSCC 96 Paper FA 8.5, 1996, discloses a prior art clock responsive latch that compensates for clock skew. The Partovi et al. latch incorporates an implicit pulse generator for extending the time during which the latch can be responsive to a data signal subsequent to an edge of a clock. The implicit pulse generator in each latch requires substantial additional circuit elements in an integrated circuit having tens of thousands of latches. The additional circuit elements in all of the latches on the chip occupy a substantial amount of space on the chip. In addition, the additional circuit elements in each latch absorb a substantial amount of power from a clock source, thereby requiring additional clock amplifiers on the chip.
The other generally employed integrated circuit clock scheme is referred to as two-phase transparent. In the two-phase transparent approach, two latches are required for each cycle of the clock wave. For a typical two-phase transparent latch clock system, between 16% and 24% of the period of a clock cycle having a frequency of 1 GHz is required for a data signal to flow through a pair of latches. Hence, the amount of time remaining for processing during the clock cycle is a relatively small percentage of each clock cycle. Thereby, an advantage of the increased data processing speed that should be associated with increased clock frequency, i.e., increased data processing speed, is not achieved. Another major disadvantage of the two-phase transparent clock arrangement is that the two latches which are required for each clock cycle increase the amount of space the latches occupy on the chip. These latch space requirements reduce the number of functions which can actually be performed by logic circuits on a particular integrated circuit chip.
It is, accordingly, an object of the present invention to provide a new and improved integrated circuit clock arrangement.
Another object of the invention is to provide a new and improved integrated circuit clock arrangement that employs only one latch per clock cycle to thereby increase the number of functions which can be performed on an integrated circuit chip relative to the prior art two-phase transparent arrangement.
An added object of the invention is to provide a new and improved integrated circuit clock arrangement having improved synchronization properties because it has a relaxed sensitivity to clock edge placement with respect to data.
An additional object of the present invention is to provide a new and improved integrated circuit chip having clock circuitry enabling the chip to operate at a relatively high frequency on a relatively large integrated circuit chip.
A further object of the invention is to provide new and improved integrated clock circuitry wherein the clock circuitry and the circuits associated therewith occupy a relatively small amount of space on the chip and the time required for data to flow through a latch is substantially less than that of a two-phase transparent arrangement.
Still another object of the invention is to provide a new and improved integrated circuit latch that achieves the clock skew advantages achieved by prior art latches incorporating an implicit pulse generator.
A further object of the invention is to provide new and improved clock circuitry that includes a logic arrangement for enabling derivation of a clock wave in response to at leas t one logic signal having a predetermined relation.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, an integrated circuit adapted to be responsive to a clock wave source and a data signal comprises a one shot having an input terminal connected to be responsive to the clock wave source. The one shot is arranged for deriving pulses in response to cycles of the clock. Each of the pulses has a finite duration, substantially less than one half of a cycle of the clock wave, but sufficiently long to overcome clock skew; in one preferred embodiment the pulse duration is about 100 picoseconds (ps), i.e., about 10% of a one GHz clock cycle. Such an arrangement allows circuitry, such as a latch, to pass the data signal to a regenerative feedback circuit.
To reduce the clock circuitry space requirements on the chip, a plurality of the latches or other circuits responsive to the clock are connected in parallel to be responsive to the pulses derived by the one shot.
Because the one shot produces a pulse that is substantially longer than the duration of an edge, the circuitry driven by the one shot can respond to data signals from different parts of the integrated circuit without the synchronization problems associated with the edge responsive clock circuitry. Because only one latch per clock wave cycle is required, volume on the chip devoted to the latch circuitry is substantially reduced relative to the two-phase transparent latch clock circuitry. In addition, the use of a one shot responsive to each cycle of the clock wave enables the flow through time of the latch circuit required to perform logic steps (i.e., overhead) to be no more than about 10%.
In certain instances, plural latch circuits are connected in cascade and located in close proximity on the integrated circuit chip. The plural latch circuits have pass through gates driven in parallel by clock pulses from the same one shot. In such an instance, there is a tendency for a data signal to flow through both of the latches during the same clock cycle. The latches, in combination with delay characteristics of combinational logic gates cascaded with the latches, overcome this tendency.
Another feature of the invention is that the one shot can be activated by combining the clock wave with bi-level signals in accordance with desired logic functions. The clock wave and the logic signals are combined in logic circuitry, which operates in accordance with the desired logic functions. For example, the
Cunningham Terry D.
Hewlett--Packard Company
Nguyen Long
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