Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-03-15
2001-03-06
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S299000
Reexamination Certificate
active
06198327
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a pulse generator, and more particularly to a pulse generator for generating a basic pulse signal activating read/write internal operations of a synchronous semiconductor memory device wherein an internal access is made by utilizing two or more clock cycles as a cycle unit.
A conventional pulse signal generator has a circuit configuration as illustrated in FIG.
1
. This conventional pulse signal generator has the following disadvantage. A pulse signal generation timing is largely delayed from input of the clock signal CLK. The conventional circuit configuration is such that a short pulse signal “B” is once generated in accordance with a logic signal “A” based upon the clock signal and the action commence signal “AC”. This means it necessary to form three logic gate stages. This short pulse generation circuit is necessary. If no short pulse generation circuit is provided, the following problems will appear. If the high level time period of the clock signal CLK is short, a reset appear due to the low level of the clock signal CLK on the delay circuit which defines the pulse width of the next stage, whereby the pulse signal may be discontinued.
The conventional pulse signal generator of
FIG. 1
has a further disadvantage as follows. A pulse width is variable depending upon variations on characteristics of the transistors due to variations in environmental conditions such as temperature and power voltage level as well as due to variations in manufacturing conditions. The conventional circuit configuration is such that the pulse width is defined by a total time of first and second delay times respectively provided by first and second delay circuits
26
and
27
. This circuit normally comprises series connections of plural stages of invertors. This delay time is just influenced by variations of the capability of the MOS transistors in the invertors.
In the above circumstances, it had been required to develop a novel pulse generator free from the above problems and generating a basic pulse signal activating read/write internal operations of a synchronous semiconductor memory device wherein an internal access is made by utilizing two or more clock cycles as a cycle unit.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel pulse generator free from the above problems.
It is a further object of the present invention to provide a novel pulse generator generating a high speed pulse.
It is a still further object of the present invention to provide a novel pulse generator capable of high speed generation of a pulse signal within a short time from input of a clock signal.
It is yet a further object of the present invention to provide a novel pulse generator capable of a pulse signal having a constant pulse width free of any variation depending upon environmental conditions such as temperature and power voltage level.
It is a further more object of the present invention to provide a novel pulse generator capable of a pulse signal having a constant pulse width free of any variation depending upon variation in characteristics of transistors due to variations of manufacturing conditions.
It is still more object of the present invention to provide a novel pulse generator capable of a pulse signal having a constant pulse width entirely depending upon a clock cycle time.
It is moreover object of the present invention to provide a novel pulse generator operable to avoid concurrent ON-states of pull-up and pull-down transistors.
It is another object of the present invention to provide a novel pulse generator capable of a pulse signal having a constant pulse width entirely depending upon a predetermined time period counted fron a pulse rising edge in synchronizing with a clock signal utilizing plural clock cycles as a cycle unit.
It is still another object of the present invention to provide a novel pulse generator capable of a pulse signal having a constant pulse width by taking a timing of a pulse falling-edge defined by a delay from a pulse rising-edge.
It is yet another object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator free from the above problems.
It is further another object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator generating a high speed pulse.
It is an additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator capable of high speed generation of a pulse signal within a short time from input of a clock signal.
It is a still additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator capable of a pulse signal having a constant pulse width free of any variation depending upon environmental conditions such as temperature and power voltage level.
It is yet an additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator capable of a pulse signal having a constant pulse width free of any variation depending upon variation in characteristics of transistors due to variations of manufacturing conditions.
It is a further additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator capable of a pulse signal having a constant pulse width entirely depending upon a clock cycle time.
It is also additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator operable to avoid concurrent ON-states of pull-up and pull-down transistors.
It is also additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator capable of a pulse signal having a constant pulse width entirely depending upon a predetermined time period counted from a pulse rising edge in synchronizing with a clock signal utilizing plural clock cycles as a cycle unit.
It is also additional object of the present invention to provide a synchronous semiconductor memory device showing reading and writing operations activated by a pulse signal generated by a novel pulse generator capable of a pulse signal having a constant pulse width by taking a timing of a pulse falling-edge defined by a delay from a pulse rising-edge.
In accordance with the present invention, ON-OFF operations of the pull-up and pull-down transistors are independently controlled so as to generate a start edge of a pulse signal in synchronizing with any one of a rising edge and a falling edge of a first cycle of the clock signal, and then generate an end edge of the pulse signal in synchronizing with any one of a rising edge and a falling edge of a later cycle than the first cycle, thereby avoiding concurrent ON-states of the pull-up and pull-down transistors, whereby the pulse generator is capable of generating the pulse signal completely depending upon a clock signal externally supplied but being independent from internal factors of the circuits. This allows a high speed and constant width pulse generation.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.
REFERENCES:
patent: 5097148 (1992-03-01), Gabara
patent: 5444407 (1995-08-01), Ganapathy et al.
patent: 5726596 (1998-03-01), Perez
patent: 5977810 (1999-
Hutchins, Wheeler & Dittmar
NEC Corporation
Nguyen Linh
Tran Toan
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