Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-12-27
2001-08-14
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S236000, C365S233100, C365S191000, C365S042000, C365S018000, C365S021000
Reexamination Certificate
active
06275416
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relate to a pulse generator circuit, particularly for non-volatile memories.
More particularly, the invention relates to a circuit for generating mutually correlated pulses which are suitable to stimulate a plurality of internal units in a non-volatile memory.
Generally, the cells of a conventional non-volatile memory are organized in a single array, and in the normal operating mode they are read by pointing to the external address that directly points to one of the cells of the memory array.
This kind of memory organization does not require particular synchronization activities internally.
However, when additional circuits, such as a counter in order to perform a plurality of sequential read operations, are introduced in order to improve the memory and provide faster operation thereof, a problem arises in synchronizing the propagation of a normal memory read stream and the occurrence of an address change, which can be triggered both internally (in the case of an increment of the counter of the memory) and externally (pointing to a random location, as occurs in the execution of a “skip” operation).
In addition to updating the new reading path, there can be other internal activities, such as preventative measures against the effects of buffer transitions (i.e., against the noise that can be generated) and feedback to the timing circuit of the memory in order to determine the end of pulses to be implemented.
In some embodiments, such as for example the memories organized in the so-called interleaved mode, the memory cells are arranged in two separate memory banks, each with its own counter.
In this last type of memory there is also another problem which is due to the fact of having to decide which of the two counters of the two banks is to be incremented, when to begin the increment, and also perform any suspension of the increment updates.
It is therefore evident that it is necessary to synchronize the various parts of the memory.
Moreover, in order to achieve the best possible performance, some of these synchronization pulses must have minimal duty cycle characteristics.
Although the duty cycle must be minimal, it must nonetheless ensure the correct generation of the pulse and its correct use.
The pulse generator circuits currently used in memories do not perform this function of generating pulses of minimal duration with the assurance of full functionality and therefore they are not suitable when one wishes to obtain high performance from a memory.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which allows to generate pulses whose duration is minimal but nonetheless sufficient to ensure correct utilization of the pulse.
Within the scope of this aim, an object of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which allows to update an internal counter of the memory.
Another object of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which allows to generate pulses which are suitable to synchronize a series of activities of the memory.
Another object of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which allows to produce such pulses according to the rules of a protocol of the interleaved type.
Another object of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which is suitable for deriving a plurality of pulses and signals for the synchronization of further parts of the memory.
Another object of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which allows interaction with the timing circuit of the memory.
Another object of the present invention is to provide a pulse generator circuit, particularly for non-volatile memories, which is highly reliable, relatively easy to manufacture and at competitive costs.
This aim, these objects and others which will become apparent hereinafter are achieved by a pulse generator circuit, particularly for non-volatile memories, characterized in that it comprises:
means for determining the instant at which a pulse for incrementing a counter of the memory is generated, said means being adapted to generate a generation start signal;
means for determining a minimum amplitude of said increment pulse which are connected to the output of said means for determining the instant at which the increment pulse is generated and are adapted to generate an increment pulse duration end signal;
first logic means for enabling the generation of said increment pulse which receive in input said increment pulse duration start and end signals; and
pulse generation means which are cascade-connected to said pulse generation enable logic means and are adapted to generate or suppress said increment pulse of the counter of the memory, also as a function of control signals received from timing means, said control signals being correlated to the current condition of said memory.
REFERENCES:
patent: 5717642 (1998-02-01), Pascucci et al.
patent: 5859810 (1999-01-01), Pascucci
patent: 5959935 (1999-09-01), Pascucci
Jenkens & Gilchrist P.C.
Nelms David
STMicroelectronics S.r.l.
Yoha Connie C.
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