Pulse generation circuit enabling its output pulse cycle to...

Details Pulse generation circuit enabling its output pulse cycle to... Pulse generation circuit enabling its output pulse cycle to...

2003-06-20

2004-11-30

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S175000

Reexamination Certificate

active

06825704

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-182590, filed on Jun. 24, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a pulse generation circuit that generates an output pulse in response to an input pulse, and more particularly to a pulse generation circuit that can shorten the output pulse cycle.
2. Description of the Related Art
In semiconductor memories such as static RAMs, the word drive circuit for driving a word line is a pulse generation circuit that generates an output pulse to the word line having a relatively heavy load in response to a predetermined control pulse. When receiving a control pulse acting as a trigger, the pulse generation circuit generates an output pulse having a higher drive capability through multi-staged inverters. The last stage of the pulse generation circuit consists of large-sized transistors to output the output pulse by driving an output load with its high drive capability. To drive the large-sized transistors in this output stage, a drive pulse having a larger drive capacity is generated from the control pulse by the multi-staged inverters.
FIG. 1
illustrates a conventional pulse generation circuit.
FIG. 2
illustrates the operational waveforms of the pulse generation circuit shown in FIG.
1
. The pulse generation circuit acting as a word line drive circuit drives a word line (not shown) connected to an output terminal OUT, in response to the control pulse at a node n
1
input into the pulse generation circuit. The word line is selected by raising the output terminal OUT and the word line returns to the non-selected state by falling the terminal OUT.
To drive the output terminal OUT having a large load capacitance, the size of the transistors in an inverter INV
3
at the output stage are made large. The control pulse is propagated being gradually converted into a pulse having a larger drive capability by multi-staged inverters INV
1
and INV
2
. The inverter INV
3
in the last stage is driven by the drive pulse generated at a node n
3
and having a relatively large drive capability.
The function desired to the word line drive circuit is the function for raising its output terminal at a timing as immediately from the leading edge (the rising edge in
FIG. 2
) of the control pulse as possible. On the other hand, it is not preferable to make the size of the transistors in the inverter of each stage larger to reduce the delay time period: because each of input load capacitance C
1
, C
2
and C
3
accompanying each inverter is also made larger and the propagation time period of the pulse becomes rather longer, and, therefore, the time period between the generation of the control pulse and the generation of the output pulse at the output terminal is made longer.
Therefore, in the conventionally proposed pulse generation circuits, the sizes of the transistors in each inverter are made imbalance. Taking an example of
FIG. 1
, the size of p-channel transistors P
1
and P
5
is made large and the size of n-channel transistors N
2
and N
6
is made small in the inverters INV
1
and INV
3
, and the size of a p-channel transistor P
3
is made small and the size of an n-channel transistor N
4
is made large in the inverter INV
2
. In this specification N means n-channel transistor and P means p-channel transistor. By arranging the sizes of the transistors as described above, the leading edge (the edge denoted by the arrow in the
FIG. 2
) of the control pulse at the node n
1
can be propagated to the next nodes n
2
and n
3
without delay and the delay of the rise edge of the output terminal OUT can be minimized. Furthermore, since the size of one transistor is large and that of another is small in the inverter in each stage, the gate capacitance C
1
, C
2
and C
3
being the input load capacitance can be decreased and the delay of propagation of a pulse can be minimized by decreasing the input load capacitance of each inverter.
However, in the above pulse generation circuit consisting of imbalance inverters, the size of the drive transistors in each stage for the trailing edge of the control pulse is small and the drive capability of those transistors is small. As a result, the slopes of the trailing edges at the nodes n
2
and n
3
are more gradual.
When the fan-out, i.e. the ratio of the output drive current to the output load to drive, of a transistor, such as the transistors P
1
, N
4
and P
5
shown in
FIG. 1
is small, the influence on the delay time period of the pulse caused by the process variation of the transistors is small. On the other hand, when the fan-out is large such as the transistors N
2
, P
3
and N
6
, the influence on the delay time period of the pulse caused by the process variation is large. As a result, trailing edge at each node corresponding to the trailing edge of the control pulse may be delayed considerably by the process variation as indicated by dt in FIG.
2
.
Since a trailing edge is an edge for the non-selected side, a small delay does not matter. However, pulse generation circuits in recent years have been demanded to narrow the time between the output pulses OUT. For example, in a word line drive circuit of an SCRAM, it is demanded to improve the performance of whole read and write operation by shortening the cycle for driving the word line. Therefore, it is necessary to advance the timing of the leading edge (rise edge) of the output pulse OUT as well as to avoid a delay, which depends on process variations, of the trailing edge (fall edge).
FIG. 3
illustrates another conventional pulse generation circuit.
FIG. 4
illustrates the operational waveforms of the pulse generation circuit shown in FIG.
3
. The pulse generation circuit shown in
FIG. 3
, which is an improvement of the one shown in
FIG. 1
, drives a NOR gate
10
at the last stage by utilizing a set pulse SET for controlling the timing of the rise of the output OUT and a reset pulse RESET for controlling the timing of the fall of the output OUT and by propagating the control pulses SET and RESET respectively via the inverters in multi-stage structures. As shown in
FIG. 3
, the NOR gate
10
at the last stage consists of transistors P
17
, P
18
, N
19
and N
20
.
The inverters in each inverter array consist of alternately combined imbalance-sized transistors and, in the figure, the large-sized transistors are depicted large and the small-sized transistors are depicted small. The leading edge of the set pulse SET is propagated through nodes n
11
, n
12
and n
13
in an inverter array INV
10
-
12
and drives a transistor P
17
of the NOR gate at the last stage to activate the output OUT. On the other hand, the leading edge of the reset pulse RESET being delayed by the amount of the output pulse width from the set pulse SET is also propagated through nodes n
14
, n
15
and n
16
in an inverter array INV
15
-
17
and drives a transistor N
20
of the NOR gate at the last stage to deactivate the output OUT.
By providing the reset pulse RESET and the inverter array INV
15
-
17
for propagating it and driving the gate
10
at the last stage, the fall of the output pulse OUT can be controlled and the delay of the fall of the output pulse can be minimized through using not the trailing edge of the set pulse SET but the leading edge of the reset pulse RESET.
By replacing the NOR gate
10
at the last stage of this pulse generation circuit with a NAND gate and an inverter, a similar pulse generation circuit can also be constituted. In such case, the phase of the control pulse is inverted.
FIG. 5
illustrates yet another conventional pulse generation circuit. The operational waveform of the pulse generation circuit shown in
FIG. 5
is illustrated in FIG.
4
. The pulse generation circuit shown in
FIG. 5
has an output stage gate circuit
12
consisting of a p-channel transistor P
30
and an N-channel transistor N
31
instead

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