Pulse generation circuit and method for synchronized data loadin

Details Pulse generation circuit and method for synchronized data loadin Pulse generation circuit and method for synchronized data loadin

1997-03-27

1999-01-12

Fears, Terrell W.

Static information storage and retrieval

Addressing

36523006, G11C 1300

Patent

active

058598103

ABSTRACT:
A memory device that includes an internal bus for the transfer of data and reporting signals from and to the memory and output pre-buffers for the transfer of data to output terminals of said memory, a pulse generation circuit for the synchronized loading of data in an output pre-buffer. Additional circuitry is provided that includes a synchronization circuit; a transmission path delay reproduction circuit for reproducing the propagation delays of the data transmitted to the output terminals; and a pre-buffer delay reproduction circuit for reproducing the propagation delays of the output pre-buffers. The synchronization circuit is adapted to synchronize the generation of at least one pulse that is synchronized with the propagation delays reproduced by the transmission path delay reproduction circuit, and the pulse is adapted to enable the loading of the data in the output pre-buffers. The synchronization of the pulse is provided as a consequence of the assured presence of the data, and the synchronous pulse is restored after a time that is equal to the delay introduced by the pre-buffer delay reproduction circuit for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of the output pre-buffers in the time interval determined by the synchronous pulse.

REFERENCES:
patent: 4797573 (1989-01-01), Ishimoto
patent: 4858197 (1989-08-01), Aono et al.
patent: 4908796 (1990-03-01), Lee et al.
patent: 5018111 (1991-05-01), Madland

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