Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1989-12-05
1991-05-28
Shepperd, John W.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
358148, 331 20, H04N 504, H03L 700
Patent
active
050199072
ABSTRACT:
Horizontal synchronizing signals included in a video signal are inputted to a PLL circuit. A counter as a divider in the PLL circuit outputs signals which are synchronized with the horizontal synchronizing signals. A gate pulse generator counts the output pulses of counter and produces a control signal for controlling a phase comparator as one of elements of the PLL circuit. The operation of phase comparator is stopped in vertical intervals in accordance with the control signal so that the phase comparator is not affected by signals which are included in the video signal and are not synchronized with the horizontal synchronizing signals. Thus, the PLL circuit produces pulses which are synchronized with the horizontal synchronizing signals in a wide frequency range.
REFERENCES:
patent: 4245251 (1981-01-01), Steckler et al.
patent: 4251833 (1981-02-01), Fernsler et al.
patent: 4253116 (1981-02-01), Rodgers, III
patent: 4780759 (1988-10-01), Matsushima et al.
patent: 4809068 (1989-02-01), Naga
patent: 4812783 (1989-03-01), Honjo et al.
Murakoshi Satoshi
Sakurai Atsushi
Kabushiki Kaisha Yamashita Denshi Sekkei
Parker Michael D.
Shepperd John W.
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