Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-06-29
2001-04-03
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S173000, C327S174000, C327S175000, C327S298000
Reexamination Certificate
active
06211709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a pulse generating apparatus applied to semiconductor circuits, and more particularly to a pulse generating apparatus generating a pulse at an output terminal in response to conditions of a control signal and an input signal.
2. Description of the Prior Art
A related art of a pulse generating apparatus typically includes a delay circuit having a plurality of inverters IV
1
to IV
3
which are connected in series to each other by using resistors R
1
and R
2
and capacitors C
1
and C
2
, so that an output signal with an inphase or antiphase to an input signal is output as depicted in
FIG. 1
(an antiphase signal is output in FIG.
1
).
As depicted in
FIG. 2
, a related art of the pulse generating apparatus having the delay circuit includes a delay circuit
10
for delaying an external input signal A
0
during a constant time, and a NAND gate
12
for performing a NAND operation by receiving both the external input signal A
0
and an output A
1
(delayed external signal) from the delay circuit
10
.
According to the related art of the pulse generating apparatus, if the input signal A
0
shown in
FIG. 3
a
is inputted to one terminal of the NAND gate
12
, and an opposite and delayed signal A
1
through the delay circuit
10
as shown in
FIG. 3
b
is inputted to the other terminal of the NAND gate
12
, a logic low pulse is generated when the input signal A
0
of a low level is changed to a high level as the result of a logical condition for the input signal combination in the NAND gate
12
, as shown in
FIG. 3
c.
FIG. 4
is a circuit diagram showing the other related art of a pulse generating apparatus. As depicted in
FIG. 4
, the other related art of the pulse generating apparatus includes a delay circuit
10
for delaying an input signal B
0
during a constant time, and a NOR gate
14
for performing a NOR gate operation upon receiving the input signal B
0
and the output signal B
1
from the delay circuit
10
.
According to the other related art of the pulse generating apparatus, the input signal B
0
as shown in
FIG. 5
a
is inputted to a terminal of the NOR gate
14
, and a delayed signal B
1
with antiphase as shown in
FIG. 5
b
is inputted to the other terminal of the NOR gate
14
, thereby generating a logic high pulse when the input signal B
0
of a high level is changed to a low level as the result of the logical condition for the input signal combination in the NOR gate
14
as shown in
FIG. 5
c.
As described above, there is a problem in that the related art of the pulse generating apparatus has been used for connecting additional capacitors having too large an area to extend the width of a required pulse signal, and other gates have been required to control the width of the pulse signal. Accordingly, the total area of the related art of the pulse generating apparatus may be increased as a result of the above reasons.
SUMMARY OF THE INVENTION
Therefore, the present invention has been devised to solve the problem involved in the prior art, and provides a pulse generating apparatus that efficiently generates a pulse embodied on a relatively small area in contrast to that of the related arts.
In order to achieve an objective of the present invention, there is provided a pulse generating apparatus outputting a pulse by receiving a first control signal, the apparatus comprising a voltage level control means for receiving said first control signal and outputting a first voltage through a first node; an output level variation means placed between said first node and a second node; a first switching means for applying a high voltage to said second node; and a second switching means for applying a low voltage to said second node; wherein said pulse is generated by a logical operation of said first control signal and a voltage at said first node.
In order to achieve the above objective, there is provided a pulse generating apparatus outputting a pulse by receiving a first control signal, the apparatus comprising a voltage level control means for receiving said first control signal and outputting a first voltage through a first node; an output level variation means placed between said first node and a second node; a first switching means for applying a voltage at said first node to said second node; and a second switching means for applying a low voltage to said second node, wherein said pulse is generated by a logical operation of said first control signal and said voltage at said first node.
In order to achieve the above objective, there is also provided a pulse generating apparatus outputting a pulse by receiving a first control signal, the apparatus comprising a voltage level control means for receiving said first control signal and outputting a first voltage through a first node; an output level variation means placed between said first node and a second node; a first switching means for applying a high voltage to said second node; and a second switching means for applying a voltage at said first node to said second node, wherein said pulse is generated by a logical operation of said first control signal and said voltage at said first node.
REFERENCES:
patent: 4578597 (1986-03-01), Soneda et al.
patent: 4626705 (1986-12-01), Raver
patent: 5151164 (1992-09-01), Blanchard et al.
patent: 5245573 (1993-09-01), Nakaoka et al.
patent: 5349245 (1994-09-01), Hughes et al.
patent: 5608667 (1997-03-01), Osawa
patent: 5675560 (1997-10-01), Ogino
Callahan Timothy P.
Cox Cassandra
Hyundai Electronics Industries Co,. Ltd.
Jacobson Price Holman & Stern PLLC
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