Pulse expanding system for microprocessor systems with slow memo

Details Pulse expanding system for microprocessor systems with slow memo Pulse expanding system for microprocessor systems with slow memo

1976-06-07

1977-09-20

Thomas, James D.

Boots, shoes, and leggings

G06F 104

Patent

active

040500969

ABSTRACT:
A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. In the digital system, data transfers on the common bidirectional data bus are accomplished without the use of a memory synchronization signal so that a special signal conductor indicating when the memory is ready to transfer data is not required. This is accomplished by logic circuitry which expands a clock signal pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily applied to the microprocessor to effect its operation.

REFERENCES:
patent: 3426328 (1969-02-01), Gunderson
patent: 3623017 (1971-11-01), Lowell
patent: 3656123 (1972-04-01), Carnevale
patent: 3757306 (1973-09-01), Boone
patent: 3919695 (1975-11-01), Gooding
patent: 3984813 (1976-10-01), Chung

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