Pulse duty deterioration detection circuit

Details Pulse duty deterioration detection circuit Pulse duty deterioration detection circuit

2006-09-12

2006-09-12

Sircus, Brian (Department: 2836)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S185000, C327S020000, C327S024000, C327S025000, C327S026000, C307S106000

Reexamination Certificate

active

07106116

ABSTRACT:
A pulse duty deterioration detection circuit with a high monitoring precision is easily provided. The pulse duty deterioration detection circuit comprises a delay circuit comprised of a general-purpose gate circuit which generates a delayed synchronous to-be-monitored clock by delaying the to-be-monitored clock by a predetermined time, a latch circuit which detects based on the to-be-monitored clock and the delayed synchronous to-be-monitored clock that a value of a decrease in a pulse width to be determined by a pulse duty of the to-be-monitored clock becomes smaller than the predetermined time, and a flip-flop circuit which samples an output signal of the latch circuit based on the to-be-monitored clock.

REFERENCES:
patent: 4399412 (1983-08-01), Rinaldi
patent: 5422918 (1995-06-01), Vartti et al.
patent: 5663665 (1997-09-01), Wang et al.
patent: 5923191 (1999-07-01), Nemetz et al.
patent: 6087868 (2000-07-01), Millar
patent: 04-294632 (1992-10-01), None
patent: 2002026704 (2002-01-01), None

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