Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-04-09
2001-07-17
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S172000, C327S291000
Reexamination Certificate
active
06262613
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a pulse duration changer and, more particularly, to a pulse duration changer for generating an output pulse signal longer in pulse duration than and an input pulse signal and a method used therein.
DESCRIPTION OF THE RELATED ART
A high-frequency pulse signal is used in electronic system, and the system components are expected to respond to the high-frequency input signal. If a system component hardly responds to the high-frequency input signal, a pulse duration changer is required for the low-speed system component without destruction of information carried thereon.
FIG. 1
illustrates the prior art pulse duration changer. The prior art pulse duration changer includes inverters
1
,
2
and
3
, NAND gates
4
and
5
and a delay circuit
6
. An input pulse signal PLS
1
is supplied to the input node of the inverter
1
, and the inverter
1
amplifies the input pulse signal PLS
1
. The input pulse signal PLS
1
is high frequency and small amplitude, and the inverter
1
increases the amplitude of the pulse signal PLS
1
. A differential amplifier serves as the inverter
1
. The output node
1
a
of the inverter is connected one input node of the NAND gate
4
, and an output node
5
a
of the other NAND gate
5
is connected to the other input node of the NAND gate
4
.
The output node
4
a
of the NAND gate
4
is branched to three signal lines, and the three signal lines are respectively connected to the input node of the delay circuit, an input node of the NAND gate
5
and an input node of the inverter
2
. The inverters
2
and
3
form an output circuit. The output circuit
2
and
3
amplifies the signal supplied from the NAND gate
4
, and shapes the wave-form of the signal. A fine output pulse signal PLS
2
is output from the output node
3
a
of the inverter
3
, and the output pulse signal PLS
2
varies the potential level in the potential range appropriate to MOS (Metal-Oxide-Semiconductor) field effect transistors.
The delay circuit
6
is implemented by a series of inverters
6
a
. Odd inverters
6
a
are connected in series, and inserted between the output node
4
a
of the NAND gate
4
and the other input node of the NAND gate
5
. Thus, the delay circuit
6
and the NAND gate
5
form a feedback loop to the input node of the NAND gate
4
. The prior art pulse duration changer is designed to change the pulse duration T1 and T6 of the input pulse signal PLS
1
to the pulse duration T3 and T8 of the output pulse signal PLS
2
(see FIG.
2
). Even if the input pulse signal PLS
1
varies the pulse duration T1 under value X1, the prior art pulse duration changer is designed to keep the pulse duration T3 of the output pulse signal PLS
2
constant (see FIG.
3
). However, the prior art pulse duration changer proportionally varies the pulse duration T3 together with the pulse duration T1 over the value X1.
Turning back to
FIG. 2
, the circuit behavior of the prior art pulse duration changer is described hereinbelow. The delay time T4 is assumed to be appropriately regulated with respect to the input pulse signal PLS
1
. In other words, the pulse duration T1 and T6 and the pulse period T9 and T10 of the input pulse signal PLS
1
are appropriate to the delay time.
The input pulse signal PLS
1
is changed from a low level to a high level at time t1, and the inverter
1
changes the output node
1
a
from the high level to the low level. The output node
1
a
at the low level causes the NAND gate
4
to enter disable state, and the NAND gate
4
changes the output node
4
a
to the high level at time t2 regardless of the potential level at the output node
5
a
. The potential level at the output node
4
a
is twice inverted, and the output circuit
2
and
3
changes the output pulse signal PLS
2
to the high level at time t3, and a time delay T2 is introduced between the rise of the input pulse signal PLS
1
and the pulse rise of the output pulse signal PLS
2
.
When the NAND gate
4
changes the output node to the high level, the delay circuit
6
starts to measure the delay time T3. However, the delay circuit
6
maintains the output node
6
b
at the high level until the expiry of the delay time T3. The NAND gate
4
directly supplies the high level from the output node
4
a
to the other input node of the NAND gate
5
, and the NAND gate
5
changes the output node
5
a from the high level to the low level.
The input pulse signal PLS
1
has the pulse duration T1. Although the input pulse signal PLS
1
is changed to the low level at time t4 and, accordingly, the inverter
1
changes the output node
1
a
to the high level, the NAND gate
5
supplies the low level to the NAND gate
4
. The output node
5
a
at the low level forces the NAND gate
4
to keep the output node
4
a
at the high level even after time t4.
The delay time T4 is expired at time t5, and the delay circuit
6
changes the output node
6
b
to the low level. Then, the NAND gate
5
changes the output node
5
a
to the high level, and the output node
5
a
at the high level allows the NAND gate
4
to change the output node
4
a
to the low level at time t6. The output circuit
2
and
3
changes the output pulse signal PLS
2
to the low level at time t7. Thus, the output pulse signal PLS
2
has the pulse duration T3, i.e., from time t3 to time t7. The pulse duration T3 is defined by the delay time T4, and is longer than the pulse duration of the input pulse signal PLS
1
. The input pulse signal PLS
1
rises at time t8, again, and the pulse period T9 is from time t1 to time t8.
The next pulse period T10 starts at time t8. Although a sequence L
2
in the pulse period T10 is basically similar to the above described sequence L
1
, the delay circuit
6
changes the output node
6
b
at different timings. As described hereinbefore, the NAND gate
4
changes the output node
4
a
to the low level at time t6. The delay circuit
6
propagates the low level toward the output node
6
b
, and the low level reaches the final inverter
6
a
at time t11. In other words, the delay circuit
6
introduces the delay time T5 into the propagation of the low level from the output node
4
a
to the final inverter
6
a
, and changes the output node
6
b
to the high level at time t11. The NAND gate
4
changes the output node
4
a
to the high level at time t9 before time t11, and the delay circuit
6
starts to propagate the high level toward the output node
6
b
. In other words, the delay circuit
6
propagates the low level and the high level at interval between time t9 and time t11. For this reason, the delay circuit
6
changes the output node
6
b
to the high level at time t11, and, accordingly, the NAND gate
5
changes the output node
5
a
to the low level as indicated by L
3
. The output node
5
a
at the low level causes the NAND gate
4
maintains the output node
4
a
at the high level regardless of the potential level at the output node
1
a.
The pulse duration T6 is from time t8 to time t12, and the input pulse signal PLS
1
falls at time t12. Accordingly, the inverter
1
changes the output node
1
a
to the high level. However, the NAND gate
4
maintains the output node
4
a
at the high level due to the output node
5
a
at the low level, and the output circuit
2
and
3
keeps the output pulse signal PLS
2
at the high level.
The high level at the output node
4
a
is propagated through the delay circuit
6
, and reaches the final inverter
6
a
at time t13. The final inverter
6
a
changes the output node
6
b
to the low level at time t13, and the NAND gate
5
changes the output node
5
a
to the high level. As a result, the NAND gate
4
changes the output node
4
a
to the low level, and, accordingly, the output circuit
2
and
3
changes the output pulse signal PLS
2
to the low level at time t14. Thus, the output pulse signal PLS
2
is in the high level from time t10 to time t14, and the pulse duration T8 is defined as shown.
The prior art pulse duration changer prolongs the pulse duration, and generates the output pulse signal PLS
2
with the
Cunningham Terry D.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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