Pulse discriminating clock synchronizer for logic derived clock

Details Pulse discriminating clock synchronizer for logic derived clock Pulse discriminating clock synchronizer for logic derived clock

1997-03-28

1999-07-06

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327162, 327141, H03K 1722

Patent

active

059202130

ABSTRACT:
A programmable device includes circuitry for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to be a reference clock signal are coupled to the circuitry for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal but only when the input signals are recognized as clocking signals. That is, the synchronizing circuits discriminate between valid input signals and spurious signals or noise.

REFERENCES:
patent: 4408333 (1983-10-01), Fujii
patent: 4973860 (1990-11-01), Ludwig
patent: 5001374 (1991-03-01), Chang
patent: 5418407 (1995-05-01), Frenkil
patent: 5572157 (1996-11-01), Takashi et al.

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