Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By pulse coincidence
Reexamination Certificate
1998-11-25
2001-04-17
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By pulse coincidence
Reexamination Certificate
active
06218869
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a pulse edge detector. Such a pulse edge detector can be used to detect whether the baud rate of pulses within a bit stream such as an asynchronous bit stream is within a required specification. Typically, the bit stream is generated by a serial interface of a computer.
BACKGROUND OF THE INVENTION
Serial interfaces are well-known in personal computer, or the like. Such serial interfaces comprise a so-called UART (Universal Asynchronous Receiver Transmitter) for generating an asynchronous bit stream comprised of data words, usually bytes, preceded by a START-bit and succeeded by a STOP-bit. The baud rate of such an asynchronous bit stream may vary. Pulse signals comprised in the bit stream can be distorted by noise picked up by a transmission line via which the bit stream is conveyed to a device receiving the asynchronous bit stream. The receiving device, which first synchronizes itself to the received bit stream, checks whether pulse signals comprised in the bit stream are within given specifications, i.e., checks the accuracy of the wave form of the pulse. The receiving device usually comprises synchronous circuitry comprised of flip flops and gate circuits. A problem might arise if, for some reason, e.g., to achieve power savings, a system clock signal of the receiving device is half the clock frequency of the personal computer generating the asynchronous bit stream. Then, a detector comprised in the receiving device cannot accurately detect whether the pulse signal is within the required specifications. So, what is needed is a baud rate detector having double resolution.
For other purposes, some form of double resolution schemes are known.
In the article “Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits”, M.
Afghahi et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, August 1991, pp. 1168-1170, discloses a double edge-triggered flip flop which responds to both edges of a clock pulse. Such a double edge-triggered flip flop can be used in a repeater inserted in a long transmission line.
In the article “Clocking Schemes for High-Speed Digital Systems”, S. H. Unger et al., IEEE Transactions on Computers, Vol. C-35, No. 10, October 1986, pp. 880-895, discloses the use of double edge-triggered D-flip flops in a clocking scheme for a high speed digital system.
In the U.S. Pat. No. 5,703,838 a Vernier delay line interpolator to be used with a coarse counter clocked by a clock signal is disclosed for measuring time intervals. By delaying a clock signal in a multiple-tapped delay line, an interpolator is obtained to be used for measuring signal time intervals with a resolution higher than the resolution of the clock signal used in the timing interval detector. Such a combination of a coarse counter and a delay line interpolator can be used in time of flight measurements to infer a particle type. Typically, resolutions as low as 25 picoseconds can be obtained.
In the Article, “1994 Symposium on VLSI Circuits”, Honolulu, Digest of Technical Papers, pp. 43-44, a high speed interface is disclosed for a multiprocessor interconnection network. To achieve higher transfer rates, among other measures, sampling of data is done on both edges of a clock signal. A receiver phase shifts a transmitter clock by 90° and uses both edges to sample incoming data.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a pulse edge detector for detecting edges of a pulse signal in a bit stream with a resolution which is double the resolution of a clock signal to be used by the detector.
It is another object of the invention to provide a pulse edge detector with simple and low cost circuitry to obtain double resolution.
In accordance with the invention, a pulse edge detector for detecting edges of a pulse signal in a bit stream, is provided which detector comprises:
a clock input terminal for a clock signal to be fed to the detector, a bit stream input terminal for the asynchronous bit stream, a synchronizing means for synchronizing the pulse signal to the clock signal, a falling edge generating means for generating a falling edge signal representing a falling edge of the synchronized pulse signal, a rising edge generating means for generating a rising edge signal representing a rising edge of the synchronized pulse signal, pulse signal phase determining means for determining a first pulse phase signal representing whether the falling edge signal falls within a first phase of the clock signal or in a second phase of the clock signal and for determining a second pulse phase signal representing whether the rising edge signal falls within the first or the second phase of the clock signal, and output generating means for generating a first detector output signal representing the first and the second pulse phase signal.
The falling and rising edge generating means being coupled to the synchronizing means, the pulse signal phase determining means being coupled to the falling and rising edge generating means and to the bit stream input terminal, and the output generating means being coupled to the pulse signal phase determining means and to the falling and rising edge generating means.
The invention is based upon the insight that input changes can be distinguished with double the resolution of the system clock by adding some simple logic, without having the need to clock a succeeding counter on both edges of the system clock.
Preferably, the pulse signal phase determining means comprises a first flip flop circuit which is clocked by an inverse clock signal. With, in principal, as compared to a single resolution detector, the addition of only one additional flip flop circuit, and some further simple logic circuitry, a simple and low cost pulse edge detector is obtained which can be used in a baud rate detector, for instance.
Preferably, the pulse signal phase determining means further comprises a second flip flop circuit, a first AND-gate and a first NOR-gate.
Preferably, the output generating means comprises a third flip flop circuit, and a first and a second OR-gate.
Preferably, the falling and rising edge generating means comprise a shared fourth flip flop circuit, and a respective second NOR-gate and second AND-gate.
Preferably, the synchronizing means comprises a fifth flip flop circuit.
Thus, the first flip flop circuit is clocked by the inverse clock signal, whereas the second, third, fourth, and fifth flip flops are clocked by the clock signal.
REFERENCES:
patent: 4773085 (1988-09-01), Cordell
patent: 5299237 (1994-03-01), Head
patent: 5455540 (1995-10-01), Williams
patent: 5485484 (1996-01-01), Williams et al.
patent: 5703838 (1997-12-01), Gorbics et al.
patent: 5761255 (1998-06-01), Shi
patent: 6118745 (2000-09-01), Hutchins et al.
By M. Afghahi et al., “Double Edge-Triggered D-Flip-Flops for High-Speed CMOS Circuits” IEEE Journal of Solid State Circuits, vol. 26, No. 8 Aug. 1991. pp. 1168-1170.
By S.H. Unger et al., “Clocking Schemes for High-Speed Digital Systems”, IEEE Transactions on Computers, vol. C-35, No. 10, Oct. 1986, pp. 880-895.
By Honolulu, Digest of Technical Papers, “1994 Symposium on VLSI Circuits” pp. 43-44.
Hongbin Hao Jerry
Kolb William W.
Nuton My-Trang
Philips Electronics North America Corp.
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