Pulse or digital communications – Synchronizers – Self-synchronizing signal
Reexamination Certificate
2000-01-19
2004-05-18
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Self-synchronizing signal
C327S142000, C327S166000
Reexamination Certificate
active
06738442
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to synchronous digital electronics. More particularly, the present invention relates to synchronizing an asynchronous signal to a local clock.
BACKGROUND OF THE INVENTION
Presently, many data systems transmit data using asynchronous transmission methods. In an asynchronous transmission system, data is sent at irregular intervals. These systems are commonly used to transmit data between computers, such as between individual computers and a mainframe. Often it is desirable to interface these asynchronous signals to synchronous systems. In order for a synchronous system to use an asynchronous signal, the asynchronous signal must be synchronized to the local clock of the synchronous system. Synchronization must be done to prevent metastability and timing exceptions from occurring in the circuitry of the synchronous system.
FIG. 2
depicts a prior art synchronization circuit
10
used to develop a synchronous output signal from an asynchronous input signal carrying data pulses. The prior art synchronization circuit
10
comprises two D-type flip-flops
16
and
18
connected in series, with each flip-flop
16
and
18
clocked by a synchronous clock
15
coupled to the clock inputs
16
CK and
18
CK. Flip-flops
16
and
18
are conventional falling-edge triggered and rising-edge triggered flip-flops, respectively. By using a falling-edge triggered flip-flop
16
followed by a rising-edge triggered flip-flop
16
(or vice versa), the signal delay introduced by the two flip-flops is one-half clock cycle compared to a full clock cycle delay if both flip-flops
16
and
18
were either rising-edge or falling-edge triggered flip-flops. The synchronization circuit
10
is capable of producing a synchronous output signal on line
14
from data pulses on the asynchronous input signal on line
12
as long as each pulse spans at least one falling edge of the synchronous clock
15
at the clock input
16
CK of falling-edge triggered flip-flop
16
. Thus, it is normally a condition for the proper operation of this circuit that the width of pulses on the input signal line
12
be greater than or equal to a clock cycle of clock
15
. Asynchronous input signal line
12
data pulses will be lost if they are present at the flip-flop input
16
D for a period of time which falls between falling edges of the synchronous clock signal
15
.
FIG. 3
depicts a prior art synchronization circuit
20
which has improved signal detection capabilities. The prior art synchronization circuit
20
is created by connecting three D-type flip-flops
26
,
28
, and
30
in series. Synchronization circuit
20
is similar to the synchronization circuit
10
of
FIG. 2
with the addition of flip-flop
30
and the use of the inverted output of flip-flop
28
to clear flip-flops
26
and
30
. Flip-flop
30
is configured as a trigger to detect the occurrence of narrow pulse-width data pulses on asynchronous input signal line
22
. The input
30
D of flip-flop
30
is tied to a high value voltage
32
and the clock
30
CK is tied to the asynchronous input signal line
22
. This arrangement allows flip-flop
30
to capture narrow pulse-width data pulses by setting the output
30
Q of flip-flop
30
high when the rising edge of a data pulse is impressed on the clock
30
CK of flip-flop
30
. However, this approach results in a circuit which requires a significant amount of recovery time before another data pulse can be detected. Between the time when the asynchronous input signal on line
22
transitions, triggering the first flip-flop
30
, and the time when this flip-flop
30
is cleared and ready to accept a new pulse, all data pulses received in the interim will be missed.
The required recovery time can be as long as two and one-half clock cycles of the synchronization clock
25
. A two and one-half clock cycle recovery time may occur in the following situation. If an incoming asynchronous clock signal data pulse on line
22
is impressed on the clock input
30
CK of flip-flop
30
, the output
30
Q of flip-flop
30
will go high. The output
30
Q of flip-flop
30
will remain high until flip-flop
30
is cleared by a clearing pulse from flip-flop
28
and flip-flop
30
will not be able to accept subsequent data pulses until the clearing pulse generated by flip-flop
28
is removed. The high signal on the output
30
Q of flip-flop
30
will be impressed on the input
26
D of flip-flop
26
. As soon as a falling edge of synchronous clock
25
is impressed on flip-flop
26
, the output of flip-flop
26
will go high. If a falling edge of synchronous clock
25
occurred just prior to receiving the data pulse, a one synchronization clock cycle delay will be introduced to a recovery period in synchronization circuit
20
. The synchronization circuit
20
then experiences the addition of a one-half synchronization clock cycle delay to the recovery period between falling edge triggered flip-flop
26
and rising edge triggered flip-flop
28
. Another synchronization clock cycle delay is added to the recovery period as the clear signal generated by flip-flop
28
clears flip-flop
26
and the low output of flip-flop
26
is propagated through flip-flop
28
to remove the clearing pulse generated at the inverted output
28
QN of flip-flop
28
. This requires a total of two and one-half synchronization clock cycles before another asynchronous signal data pulse may be received.
The prior art approaches to signal synchronization are not suitable for many applications. For example, if the data pulses of an asynchronous input signal are narrow or occur at a greater frequency than once every two and one-half clock cycles of the synchronous clock, the prior art approaches are unable to assure detection of all the pulses on the input signal.
SUMMARY OF THE INVENTION
The present invention discloses a synchronization method and apparatus capable of detecting and synchronizing asynchronous signal data pulses while minimizing the recovery time required after each data pulse. The invention accomplishes this by passing individual data pulses alternately through two parallel synchronization circuits and combining the output of the parallel synchronization circuits to create a single synchronous signal which is representative of the data pulses of the asynchronous signal.
REFERENCES:
patent: 4412342 (1983-10-01), Khan et al.
patent: 4899351 (1990-02-01), Bonke
patent: 4973860 (1990-11-01), Ludwig
patent: 5155745 (1992-10-01), Sugawara et al.
patent: 5331669 (1994-07-01), Wang et al.
patent: 5959915 (1999-09-01), Kwon et al.
patent: 6393081 (2002-05-01), Whetsel
Agere Systems Inc.
Ha Dac V.
Synnestvedt & Lechner LLP
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