Pulse density modulation circuit (parallel to serial) comparing

Details Pulse density modulation circuit (parallel to serial) comparing Pulse density modulation circuit (parallel to serial) comparing

1993-02-01

1994-08-09

Callahan, Timothy P.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using particular code or particular counting sequence

341 50, 341 53, 341101, 377 39, H03K 2114

Patent

active

053373383

ABSTRACT:
A pulse density modulation circuit has a counter which produces a most significant bit through a least significant bit output based on a clock input. The circuit also has a comparator with two sets of most significant bit through least significant bit inputs that produces an output based on a comparison of the two sets of inputs. The first set of comparator most significant bit through least significant bit inputs receives respectively a most significant bit through a least significant bit of an input reference signal. The second set of comparator most significant bit through least significant bit inputs receives the counter most significant bit through least significant bit output in a non-sequential bit order. The non-sequential bit order can be a bit reversed order wherein the counter most significant bit through least significant bit output are respectively connected to the comparator least significant bit through most significant bit input. The circuit may further filter the comparator output to provide a resultant analog output signal.

REFERENCES:
patent: 3719897 (1973-03-01), Tarr
patent: 4967283 (1990-10-01), Uchiyama et al.
patent: 5053769 (1991-10-01), Landmann
patent: 5095279 (1992-03-01), Quan et al.

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