Pulse delay circuit having two comparators

Details Pulse delay circuit having two comparators Pulse delay circuit having two comparators

1990-09-19

1993-01-26

Sikes, William L.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307601, 307358, 328 55, H03K 5159

Patent

active

051824809

ABSTRACT:
A pulse signal delay circuit comprises an input node for receiving a first pulse signal, an output node for outputting a second pulse signal, a delay circuit for delaying the first pulse signal to provide a delayed signal, a first comparator for comparing the first pulse signal with the second pulse signal to output a first comparison result, and a second comparator for comparing the first comparision result with the delayed signal to output a second comparison result.

REFERENCES:
patent: 3979683 (1976-09-01), Ikeda
patent: 4322642 (1982-03-01), Sugasawa
patent: 4339727 (1982-07-01), Kage et al.
patent: 4469082 (1984-09-01), Nishitoba et al.
patent: 4975657 (1990-12-01), Eastmond
Patent Abstracts of Japan, vol. 6, No. 259, dated Dec. 17, 1982.
Patent Abstracts of Japan, vol. 11, No. 363, dated Nov. 26, 1987.

Affiliated with

Also associated with

Rating

Pulse delay circuit having two comparators does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pulse delay circuit having two comparators, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pulse delay circuit having two comparators will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1414427