Pulse delay circuit and A/D converter including same

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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Details

C327S182000

Reexamination Certificate

active

07932848

ABSTRACT:
The pulse delay circuit includes a plurality of delay units connected in series or in a ring, each of the delay units being constituted of at least one inverter gate circuit grounded to a ground line, and configured to delay a pulse signal passing therethrough by a delay time thereof depending on an input signal applied thereto, and a capacitor connected between a signal line through which the voltage signal is applied to each of the delay units and the ground line. The capacitor serves as a current source to supply a current which each of the delay units consumes to invert a state thereof.

REFERENCES:
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patent: 5477196 (1995-12-01), Yamauchi et al.
patent: 6771202 (2004-08-01), Watanabe et al.
patent: 6879278 (2005-04-01), Watanabe et al.
patent: 7248197 (2007-07-01), Watanabe
patent: 7292176 (2007-11-01), Chen et al.
patent: 7679333 (2010-03-01), Goto
patent: 05-259907 (1993-10-01), None
patent: 07-183800 (1995-07-01), None
patent: 2004-007385 (2004-01-01), None
patent: 2004-357030 (2004-12-01), None
patent: 2005-322327 (2005-11-01), None
patent: 2007-006368 (2007-01-01), None
patent: 2007-006369 (2007-01-01), None
Office action dated Aug. 24, 2010 in corresponding Japanese Application No. 2008-316969.

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