Pulse clock/signal delay apparatus and method

Details Pulse clock/signal delay apparatus and method Pulse clock/signal delay apparatus and method

2002-01-07

2004-02-24

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000, C327S291000

Reexamination Certificate

active

06696875

ABSTRACT:

BACKGROUND OF THE INVENTION
Electrical Networks
An electrical network consists of signal nodes connected by electrically active elements. The electrically active elements include conductors, linear passive elements and linear and non-linear active elements. A given network is partially described by the kinds of elements involved and the network geometry, i.e., the manner in which the various elements are grouped and interconnected at their terminals. Passive elements such as conductors, resistors, capacitors and inductors may be interspersed with active elements such as transistors, gates, integrated circuits and the like.
All of these elements may be considered branches of the network. The geometry of a network is described in schematic form by the nodes to which two or more terminals of the elements are connected. The electrical conductors of the network are themselves elements or branches of the network.
One portrayal of a network shows the geometrical interconnection of elements only, and takes the form of a graph; i.e. each element of the network is represented as a line having two small circles at either end denoting the terminals of the elements connected at a node.
In digital logic networks (circuits), active elements (devices) may have terminals that are bi-directional (sometimes operating as an input and sometimes as an output) but are generally unilateral, i.e., signal transmission for related terminal pairs proceeds in one direction only, e.g. from an input terminal to an output terminal. Even bi-directional terminals exhibit unilateral behaviour for certain time periods, e.g., during a portion of a system clock cycle or cycles when they are designated as input or output.
Complex Elements in Networks
Complex elements, such as logic arrays, microprocessors and memory components are generally represented as rectangular boxes with multiple lines extending to small circles denoting terminals. The lines are annotated to represent input and output logic variable names. For example, in
FIG. 1
, n
1
, n
2
indicate signal node n
1
and signal node n
2
, l(
1
,
2
) indicates a signal link or path between nodes
1
and
2
. The links l(
1
,
2
) may be composed of any combination of passive and active elements connected in series-parallel combinations. That is, signal nodes n
1
and n
2
are connected by signal paths l(
1
,
2
) that may represent a simple conductor or may represent a complex bi-bilateral element such as a combined microprocessor/logic array or a series-parallel combination of many different kinds of each. Let S[r] represent all signal paths of interest for the network of FIG.
1
.
Networks may be built from any one of a number of particular logic families, e.g., TTL (transistor-transistor logic), RTL (resistor-transistor logic), ECL (emitter-coupled logic), CMOS complementary-insulated gate and the like. Basic active elements, viz. logic functions, such as NAND, NOR, AND, INVERT gates, pass transistors are generally interconnected to form the complex elements described above which in turn are interconnected to form still more complex elements.
Network Element Delay
Complex logic elements may be characterised to a first order by a plurality of input and output terminals, each having a respective logic threshold. The logic thresholds at input and output (the voltage level or current level at an input or output terminal which defines the transition between a logic one and zero) may be the same or different. A logic function of a complex element, i.e., the logical response at an output from a logic transition at one or more activating inputs, typically can also be characterised as having a time interval or propagation delay through the active element or function between a logic transition of an activating signal at an input and a logic transition of a responsive signal (if any) at an output. The propagation delay is the time interval between the logic transition of the input signal at an input terminal and a corresponding logic transition of a respective responsive signal at a corresponding output terminal. The propagation delay of a branch or element is the interval or span of time between an input signal transition (for digital circuits, a logic transition) originating at one terminal of an element or branch until the occupancy of a corresponding output signal transition (or edge) at another terminal (the output terminal) of the element or branch by the propagation of the effect of the input signal through the element or branch.
A multiple terminal active element may have a multiplicity of signal edge delay time delay intervals between a particular pair of terminals associated with different functions or state transitions. Typically the design of electrical network systems will take into account a worst-case delay interval for such terminal pairs.
Another important feature of high-speed digital networks is the topology of the physical network. There is generally little correspondence between the topology of the schematic or network graph and the topology of the actual physical layout of the circuit elements and interconnections. Frequently, in translating a complex circuit design from schematic to printed circuit board (PCB) layout, the physical length (and consequently the electrical length or delay time) of the conductor traces between different nodes (terminals) of logic elements (due to the excessive signal edge delays caused by the interconnect) impacts the performance of the system so significantly, that the layout must be redesigned. Redesigning the layout adds significant cost and schedule delays in the process of introducing a new product to the marketplace. There is no assurance that a re-layout will not introduce another critical delay limitation in the same or some other path.
The propagation delays of circuit elements themselves can also be problematic. Components made by different component manufacturers may have inherent propagation delay times between input and output terminals that have different probability distributions. Worst case design to cover different ranges of propagation delay tend to decrease performance for lower cost devices, or increase cost for higher performance (i.e., faster or tighter distribution) devices. Some physical layout design tools are available from Computer Aided Design Tool services and manufacturers that are typically used to analyse the performance and timing of topological layouts for instances of limitations caused by the delay issues discussed above. Once a problem is identified, components may be relocated and a timing analysis run again. This layout-analysis step often can become a loop procedure repeated several times until the performance is satisfactory.
The propagation delays between input signal transitions and output signal transitions of logic elements and of the interconnect (branches) between nodes (terminals) is one very significant feature of high speed networks. A series connection of two or more branches forms a signal path having an associated cumulative signal propagation delay.
The cumulative propagation delay, t
d
, of a signal path composed of a series of branches, l≦k≦K, is sometimes approximated by computing
t
d
&Sgr;t
k
,
the simple arithmetic sum of the propagation delays of the series branches, t
k
.
Another useful approximation is the geometric sum of the individual branch propagation delays:
t
d
={square root over (&Sgr;t
k
2
)}.
Generally, the total branch delay intervals lie between these two approximations.
Practical Considerations to Signal Delays
For complex, high performance networks, such as computer motherboards and microprocessor chips the delay time delay interval of the interconnect (i.e., wires and PCB traces) can have a significant impact on the maximum speed of the network. Particularly as the operational cycle time of computer chips and boards increases to 300-400 and 500 MHz the length of half a clock period is decreased from 15 to 12.5 to 10 ns. Since the speed of an electrical signal on a PCB can be about 1.5 ns per foot, for an 18 inch PCB

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