Pulse-based high-speed low-power gated flip-flop circuit

Details Pulse-based high-speed low-power gated flip-flop circuit Pulse-based high-speed low-power gated flip-flop circuit

2006-12-26

2006-12-26

Tra, Quan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S202000

Reexamination Certificate

active

07154319

ABSTRACT:
A high-speed gated flip-flop includes a latch configured to generate a data output signal (Q) in response to a data input signal (D) and a pair of true and complementary clock pulses (GCP,GCPB). These clock pulses are provided by a clock generator responsive to a periodic clock signal (CK). A control circuit is also provided. The control circuit is coupled to a feedback node (ND2) in the pulse generator. The control circuit configured to selectively enable the pulse generator in response to an enable signal (/EN). The pulse generator is configured so that an active transition of the true clock pulse (GCP) is fed back to the feedback node (ND2) in a manner that resets the pulse generator and terminates the true and complementary clock pulses in-sync with the active (e.g., low-to-high) transition of the true clock pulse (GCP).

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