Modulators – Pulse or interrupted continuous wave modulator – Pulse amplitude modulator
Patent
1996-11-20
1998-03-10
Grimm, Siegried H.
Modulators
Pulse or interrupted continuous wave modulator
Pulse amplitude modulator
375268, 375300, 455108, H03K 702, H04L 2704
Patent
active
057266093
DESCRIPTION:
BRIEF SUMMARY
This application is the national phase of international application PCT/F195/00268, filed May 18, 1995 which designated the U.S.
The invention relates to a method and to an apparatus for forming a pulse amplitude modulated (PAM) signal.
A recurrent problem particularly in so-called HDSL modems (High Speed Digital Subscriber Line) is that a timing signal received from outside the transmitter contains abundant jitter. Optimal elimination of jitter is called for as at high symbol rates even minor jitter will impair performance. Requirements for timing accuracy are especially high when the so-called echo cancellation technique is used. This is because high accuracy is required of signal values at echo cancellation points, as even the slightest ambiguity an timing may cause too big an error in the signal value.
A qualitatively superior clock signal may be generated by means of a phase lock which adequately damps out jitter (i.e. which is sufficiently narrow-band). A phase lock may be realized as a digital or an analog phase look with a voltage controlled crystal oscillator. A disadvantage of a digital phase lock is, however, that it generates phase hope that are equal in length to one cycle of the master clock being used. Even less than 10 ns phase hops are called for in HDSL modems, whereby an over 100 MHz master clock frequency would be required. With present technology, this is, however, a slightly too high a frequency. Similarly, phase hops of 5 ns would require a 200 MHz clock, etc. The disadvantage of a voltage controlled crystal oscillator is that it cannot be completely integrated into a digital circuit. In addition to the VCO, a loop filter has to be realized by analog technique.
Instead of using an external clock signal, the clock signal may be generated inside the modem. With a multi-bit-rate modem, fractions must often be used as divisors (in addition to integers) in order to obtain all pertinent clock frequencies by division from the frequency of the internal clock oscillator of the modem. This will cause jitter for the clock signal to be generated, i.e. the case is principally similar to that of an external clock signal.
The main object of the present invention is to provide a method and an apparatus guaranteeing an accurate timing in the above cases.
The idea of the invention is to store in a memory a pre-filtered waveform of a PAM pulse to be transmitted and multiply the sample values, read from the memory at the rate of a fixed-frequency clock signal, by a factor to be modified according to the symbol being transmitted.
The solution of the invention provides integration of an implementation with accurate timing into a completely digital circuit. The desired accuracy is obtained by choosing an adequate bit accuracy.
The bandwidth of many transmission paths is also in some way limited, and a pulse to be transmitted must be filtered. With the method of the invention digital filtration may easily be integrated into the same apparatus, whereby only a simple analog filter is needed for eliminating harmonic spectrum components.
In the following the invention and its preferred embodiments will be described in greater detail with reference to examples in accordance with the accompanying drawings, in which
FIG. 1a illustrates the principle of a direct digital synthesis,
FIG. 1b shows a signal at an output of a phase accumulator of the apparatus of FIG. 1,
FIG. 1c shows a signal at an output of a sine table of the apparatus of FIG. 1,
FIG. 2 shows the principle of digital pulse amplitude modulation of the invention,
FIG. 3 shows a preferred embodiment of the apparatus of the invention,
FIG. 4 shows formation of a phase increment signal used in the apparatus of FIGS. 2 and 3.
To illustrate the invention, FIG. 1a first shows the principle of direct digital synthesis (DDS). In the DDS system a phase increment signal M and a clock signal f.sub.c are first fed into a phase accumulator 11. The phase accumulator comprises an adder and a latch, connected in succession, and the phase accumulator adds the value M t
REFERENCES:
patent: 4992743 (1991-02-01), Sheffer
patent: 5583467 (1996-12-01), Loewenguth et al.
Grimm Siegried H.
Nokia Telecommunications Oy
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