Pulse amplifier with low duty cycle errors

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit

Reexamination Certificate

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Details

C327S262000, C327S558000, C327S174000, C327S180000, C330S010000, C330S260000

Reexamination Certificate

active

06208199

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a low power pulse amplifier, and more particularly to a low power pulse amplifier with a low duty cycle error at high input levels.
BACKGROUND OF THE INVENTION
The duty cycle requirements for pulse amplifiers of this type excludes the use of single-ended amplifiers since clipping at higher amplitudes results in different clip levels and delays in the positive and negative directions.
Typically, for a single-ended input signal, an ordinary differential stage consisting of a differential pair of transistors produces asymmetrical delays in the positive and negative directions of the input signal if the input signal is large. The main reason for this is that the common source node for the differential pair will change its potential differently between large positive and large negative input signals.
When the input signal turns off the input transistor, the voltage of the common source node only changes a small amount due to the doubled current in the other transistor. In the other direction the common source node shorts to the output node and changes a substantial amount. One solution to this problem is to reduce the absolute delay times by increasing bandwidth. But this solution comes at the expense of increased current consumption.
An object of the present invention is to provide an improved pulse amplifier.
SUMMARY OF THE INVENTION
According to the present invention there is provided a pulse amplifier comprising an input for receiving input signals, an output, and a plurality of fully differential amplifier stages between said input and output arranged to ensure more symmetrical delays in positive and negative directions of the input signals.
In accordance with the invention fully differential gain stages, that is differential amplifiers with differential inputs and differential outputs, give more symmetrical delays and reduce the problem.
In a preferred embodiment, each fully differential amplifier stage comprises first and second transistors forming a differential pair and having a common node, a pair of load transistors in parallel with the respective first and second transistors, and a limiting circuit for limiting the voltage swing of the common node to a substantially constant voltage for large input signals. It is however possible to place the load transistors in series with the transistors of the differential pair.
The invention also preferably includes a biasing network and an offset canceling network.


REFERENCES:
patent: 3772604 (1973-11-01), Hogg et al.
patent: 5469097 (1995-11-01), Ho
patent: 5512848 (1996-04-01), Yaklin
patent: 6054886 (2000-04-01), Opris et al.
patent: 0 358 518 A1 (1990-03-01), None
patent: 0 451 378 A1 (1991-10-01), None
patent: 2258779 (1993-02-01), None
patent: WO 95/22202 A1 (1995-08-01), None
patent: WO 95/22206 A1 (1995-08-01), None

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