Pullup resistance control input circuit and output circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307451, 307548, 307579, H03K 1716, H03K 1990

Patent

active

052162923

ABSTRACT:
In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q.sub.1) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.DD) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a low logical level, the pullup transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to increase the potential of the input end of the inverter (11).

REFERENCES:
patent: 4553045 (1985-11-01), Murotani
patent: 4612466 (1986-09-01), Stewart
patent: 4785203 (1988-11-01), Nakamura
patent: 4961010 (1990-10-01), Davis
patent: 5036222 (1991-07-01), Davis
patent: 5057711 (1991-10-01), Lee et al.

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